30 December 2016 Technology for fabrication of sub-20 nm silicon planar nanowires array
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Proceedings Volume 10224, International Conference on Micro- and Nano-Electronics 2016; 102241V (2016) https://doi.org/10.1117/12.2267112
Event: The International Conference on Micro- and Nano-Electronics 2016, 2016, Zvenigorod, Russian Federation
Abstract
The results presented on Silicon one-dimensional structures fabrication which are promising for application in nanoelectronics, sensors, THz-applications. We employ two-stage technology of precise anizotropic plasma etching of silicon over e-beam resist and isotropic removal of thermally oxidised defected surface layer of silicon by wet etch. As first the process for nano-fins fabrication on SOI substrate was developed. HSQ resist was used as a negative-tone electron beam resist with good etch-resistance, high resolution and high mechanical stability. The etching was performed by RIE in mix of SF6 + C4F8. plasma. By changing the ratio SF6:C4F8, the sidewall profile angle can be controlled thoroughly. Next step to minimize lateral size of structures and reduce impact of surface defects on electron mobility in core of nanowires was the application of surface thermal oxidation to defected layer. It was used for selective removal of damaged silicon layer and polymer residues. Oxidation was performed with controlled flow of dry oxygen and water vapour. Oxidation rate was precisely controlled by ex-situ spectral ellipsometry on unpatterned chips As a result the arrays of planar sub-20 nm Silicon nanowires with length in the range 200 nm – 500 um were made.
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Andrey V. Miakonkikh, Andrey A. Tatarintsev, Alexander E. Rogozhin, Konstantin V. Rudenko, "Technology for fabrication of sub-20 nm silicon planar nanowires array", Proc. SPIE 10224, International Conference on Micro- and Nano-Electronics 2016, 102241V (30 December 2016); doi: 10.1117/12.2267112; https://doi.org/10.1117/12.2267112
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