10 February 2017 A 10Gb/s partial response equalizer in 0.18μm CMOS using duobinary signaling
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Proceedings Volume 10250, International Conference on Optical and Photonics Engineering (icOPEN 2016); 102500W (2017) https://doi.org/10.1117/12.2266824
Event: Fourth International Conference on Optical and Photonics Engineering, 2016, Chengdu, China
Abstract
This paper presents a 10Gb/s partial response (PR) equalizer in 0.18μm CMOS technology. By incorporating a reshaping filter with high-frequency emphasis and the intrinsic roll-off bandwidth of the channel, a duobinary signal is available at the receiver, reducing the bandwidth requirement of high speed communication. To enhance the performance of the PR equalizer, a two-path oversampling technique is used to cope with the time delay variations due to different process corners. Additionally, adjustable capacitance and load calibration technique are also applied to eliminate the process variations further. The chip area including I/O pads occupies 0.835×0.715mm2 and the power consumption is about 224mW under 1.8V power supply. Post simulation results show that the proposed equalizer works properly at 10Gb/s and more than 70% eye opening can be obtained.
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Chao Zheng, Chao Zheng, Qingsheng Hu, Qingsheng Hu, } "A 10Gb/s partial response equalizer in 0.18μm CMOS using duobinary signaling", Proc. SPIE 10250, International Conference on Optical and Photonics Engineering (icOPEN 2016), 102500W (10 February 2017); doi: 10.1117/12.2266824; https://doi.org/10.1117/12.2266824
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