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Abstract
As design rules shrink to meet the needs of advanced chips, the allocation of allowable errors between sources gets ever more critical. This paper will examine the error sources and budgets for current technologies and project the requirements for future 64 and 256 megabit generations.

The emphasis will be on overlay and critical dimension as a function of design rule generation for the photomask, the photolithographic process and the etching process.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
John Canning and Gilbert V. Shelden "Lithography error budget", Proc. SPIE 10273, 64-to 256-Megabit Reticle Generation: Technology Requirements and Approaches: A Critical Review, 1027304 (1 January 1994); https://doi.org/10.1117/12.177437
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