Abstract
This paper discusses digital electronic VLSI architectures for emulating neural networks. The major advantage of digital implementation is its flexibility, which, because of “Amdahl’s Law,” is more valuable than raw speed. As an example of a digital architecture, Adaptive Solution’s CNAPS1, architecture is discussed in detail. CNAPS consists of a single-instruction, multiple-data (SIMD) or "data parallel” array of simple DSP-like processor nodes. By using low-precision arithmetic, an optimized processor architecture, and simple broadcast communication, many processors can fit on a one silicon chip, thus allowing cost-effective, high-performance computation for image processing and pattern recognition applications.

The last half of the paper discusses mapping several algorithms to the CNAPS architecture. Algorithms discussed include back-propagation, Fourier transforms, JPEG image compression, and convolution.
© (1994) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Dan Hammerstrom, "Digital electronic neural networks", Proc. SPIE 10277, Adaptive Computing: Mathematics, Electronics, and Optics: A Critical Review, 1027707 (1 March 1994); doi: 10.1117/12.171196; https://doi.org/10.1117/12.171196
PROCEEDINGS
20 PAGES


SHARE
RELATED CONTENT

Autowave media and neural networks
Proceedings of SPIE (November 01 1991)
Analog storage of adjustable synaptic weights
Proceedings of SPIE (September 16 1992)
Analog CMOS contrastive Hebbian networks
Proceedings of SPIE (September 16 1992)
Very-low-noise switching-free CNN-based adder
Proceedings of SPIE (November 02 1999)

Back to Top