A laser scanning microscope offers a non-destructive technique to locate and analyze latch-up in an IC. We have developed an advanced, fully automated latch-up analyzer coupled with the CAD system used for IC design. It consists of a laser scanning microscope, a x-y table for chip scanning, a monitor TV and a microprocessor based system for control of the test sequence and data analysis. Latch-up sensitivity is measured by stepwise increase of laser beam power using an acousto-optical modulator. The monitoring of the beam position and the modulator voltage while scanning the laser spot over the IC surface and the resulting current changes in the device's power supply locate the latch-up zone and its sensitivity. The sensitive regions found are overlaid graphically over the IC layout data to provide a redesign posibility. As an application example we consider a CMOS A/D converter IC and explain the system performance.