In this paper, we analyze the computational requirements of the key MPEG-2 decoding functions from the instruction level. We use a generic sequential processor model with a RISC-like instruction set to map the tight loop of the key functions to machine instructions. We then extend our processor model to instruction-level parallel (ILP) architectures and present the speed improvement of each key function on two different ILP features and as the degree of parallel processing is increased.
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Woobin Lee, Yongmin Kim, "MPEG-2 video decoding on programmable processors: computational and architectural requirements," Proc. SPIE 10282, Standards and Common Interfaces for Video Information Systems: A Critical Review, 102820F (25 October 1995);