25 October 1995 MPEG-2 video decoding on programmable processors: computational and architectural requirements
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Design of a cost-effective microprocessor architecture for MPEG video decoding requires not only the analysis of MPEG algorithms in terms of the raw number of additions or multiplications, but more importantly, a careful study of mapping those algorithms to the target processor architecture at the instruction level. Even though smart compilers can generate fast and compact codes that rival the hand-optimized code on sequential algorithms, a more accurate evaluation of the processor performance on parallel algorithms such as the core functions in the MPEG-2 decoding is achieved by hand-optimizing the tight loop.

In this paper, we analyze the computational requirements of the key MPEG-2 decoding functions from the instruction level. We use a generic sequential processor model with a RISC-like instruction set to map the tight loop of the key functions to machine instructions. We then extend our processor model to instruction-level parallel (ILP) architectures and present the speed improvement of each key function on two different ILP features and as the degree of parallel processing is increased.
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Woobin Lee, Yongmin Kim, "MPEG-2 video decoding on programmable processors: computational and architectural requirements", Proc. SPIE 10282, Standards and Common Interfaces for Video Information Systems: A Critical Review, 102820F (25 October 1995); doi: 10.1117/12.227954; https://doi.org/10.1117/12.227954

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