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7 August 2017 Reducing hardware in FPGA-based Mealy FSM
Małgorzata Kołopieńczyk, Larysa Titarenko, Kamil Mielcarek, Alexander Barkalov
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Proceedings Volume 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017; 104451G (2017) https://doi.org/10.1117/12.2280407
Event: Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2017, 2017, Wilga, Poland
Abstract
This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.
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Małgorzata Kołopieńczyk, Larysa Titarenko, Kamil Mielcarek, and Alexander Barkalov "Reducing hardware in FPGA-based Mealy FSM", Proc. SPIE 10445, Photonics Applications in Astronomy, Communications, Industry, and High Energy Physics Experiments 2017, 104451G (7 August 2017); https://doi.org/10.1117/12.2280407
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Field programmable gate arrays
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