16 October 2017 Adopting rigorous verification flow in fabrication of silicon photonic devices
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Abstract
Throughout this report, we demonstrate the benefits of lithography simulation for the fabrication of the photonic devices using a rigorous verification flow. In our case, we report the application rigorous lithography simulation to predict the fabrication imperfections of silicon photonic devices during the lithography process. Resist calibration has been performed, with both FEM CD and resist profile simulation results matching well with the wafer results for the design rule patterns. SEM overlay proves that the simulation contours agree with the wafer images for the design rule test patterns.
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Siti Noor Aisyah Binti Yahya, Siti Noor Aisyah Binti Yahya, Mogana Sundharam A/L Sathisivan, Mogana Sundharam A/L Sathisivan, Chuanhai Li, Chuanhai Li, Jinhua Pei, Jinhua Pei, Yu Chen, Yu Chen, } "Adopting rigorous verification flow in fabrication of silicon photonic devices", Proc. SPIE 10451, Photomask Technology, 1045106 (16 October 2017); doi: 10.1117/12.2280485; https://doi.org/10.1117/12.2280485
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