14 February 2018 Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme
Author Affiliations +
Abstract
We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. Shinya, T. Ishihara, K. Inoue, K. Nozaki, S. Kita, M. Notomi, "Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme ", Proc. SPIE 10551, Optical Data Science: Trends Shaping the Future of Photonics, 1055106 (14 February 2018); doi: 10.1117/12.2296842; https://doi.org/10.1117/12.2296842
PROCEEDINGS
6 PAGES


SHARE
Back to Top