17 May 1989 Digital-Analog-Hybrid Neural Simulator: A Design-Aid For Custom-VLSI Neurochips
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Proceedings Volume 1058, High Speed Computing II; (1989) https://doi.org/10.1117/12.951677
Event: OE/LASE '89, 1989, Los Angeles, CA, United States
A high speed neural network simulator and its use for the dynamics and performance analysis of feedback neural architectures are described. The simulator is based on a semi-parallel, analog-digital hybrid architecture which utilizes digital memories to store synaptic weights and analog hardware for high speed computation. A breadboard system with 8-bit gray scale synapses, designed and built at JPL, is successfully serving as a valuable design test-bed for the development of fully parallel, analog, custom VLSI neurochips, currently underway at JPL. The breadboard hybrid simulator indeed allows a detailed evaluation of hardware potential and limitations in implementing full analog operations in such chips. As an example, the paper presents an analysis of the stability and convergence behavior of a feedback neural network applied to the "Concentrator Assignment Problem" in combinatorial optimization, as studied on the analog-digital hybrid simulator. This has already resulted in a VLSI custom design of a fully parallel, analog neuroprocessor with a powerful "analog prompting" feature, for the high-speed, multiparameter optimization function.
© (1989) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
A. Moopenn, A. P. Thakoor, T. Duong, "Digital-Analog-Hybrid Neural Simulator: A Design-Aid For Custom-VLSI Neurochips", Proc. SPIE 1058, High Speed Computing II, (17 May 1989); doi: 10.1117/12.951677; https://doi.org/10.1117/12.951677


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