17 May 1989 Memoryless Bit-Serial Processing Element For Highly Parallel Computing
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Proceedings Volume 1058, High Speed Computing II; (1989) https://doi.org/10.1117/12.951688
Event: OE/LASE '89, 1989, Los Angeles, CA, United States
Abstract
Simple bit-serial processors are useful in the construction of highly parallel computing architectures where thousands of individual processors may be combined to create very powerful machines. Conventional bit-serial processors are limited by several factors including a von Neumann bottleneck associated with their local memory segment, limited speed of each processor, and very high control bandwidth requirements. The memoryless Bit-Serial Pipeline (BISEP) processing element replaces the conventional local memory segment with a parallel pipeline structure through which data is piped in systolic fashion. In addition to overcoming some of the conventional processor's limitations, the BISEP architecture has higher performance then conventional processors in many applications and is more easily fabricated with some silicon technologies such as gate arrays.
© (1989) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bill Wehner, "Memoryless Bit-Serial Processing Element For Highly Parallel Computing", Proc. SPIE 1058, High Speed Computing II, (17 May 1989); doi: 10.1117/12.951688; https://doi.org/10.1117/12.951688
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