17 May 1989 Parallel Recirculating Pipeline For Signal And Image Processing
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Proceedings Volume 1058, High Speed Computing II; (1989); doi: 10.1117/12.951663
Event: OE/LASE '89, 1989, Los Angeles, CA, United States
Abstract
Current image analysis and image understanding applications in DoD systems require very high performance image pixel processing in real time. To attain the necessary performance within stringent system size, weight, and power constraints requires special-purpose parallel processing hardware architectures. At the same time, it is desirable to retain as much programmability as possible in order to rapidly adapt the hardware to new applications or evolving system requirements. The Parallel Recirculating Pipeline processor uses techniques adopted from image algebra and mathematical morphology to provide a low-cost, low-complexity, high-performance architecture that is suitable for silicon implementation and programmable in high-order languages.
© (1989) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Bill Wehner, "Parallel Recirculating Pipeline For Signal And Image Processing", Proc. SPIE 1058, High Speed Computing II, (17 May 1989); doi: 10.1117/12.951663; https://doi.org/10.1117/12.951663
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KEYWORDS
Image processing

Image segmentation

Process control

Signal processing

Imaging arrays

Parallel computing

Computer programming

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