Over the past few decades, the semiconductor industry has been employing size shrinkage as the most efficient method to reduce production cost in order to fit more and more transistors on one unit area. Each size shrinkage has been categorized as either node or generation by the theoretical gate length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). In the advanced node, such as the sub-10nm node, size shrinkage is not applicable due to the physics limitation of 193nm immersion lithography. Therefore, alternative methods, extreme ultra violet lithography (EUV) and multi-patterning solutions based on 193nm immersion lithography, are attracting significant attentions in research and development across the industry. Among the various patterning techniques, the front-runner is self-aligned multiple patterning (SAMP). This technique uses the sidewall spacer formation as a transferable pattern and achieve pitch halving purpose. By repeating this technique, the pitch halving can be executed countless times, theoretically; this gives this technique an advantage over other techniques. However, due to the device design and sidewall formation in both sides, an additional line cut step is required to be performed to fulfill the requirements of isolation and N/P boundaries. The most challenging pattern in the line cut step is the single line cut without defect formation.