19 March 2018 Process development of a maskless N40 via level for security application with multi-beam lithography
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Abstract
The maskless electron beam lithography system, based on massively parallel electron-beam writing strategy has the ability for low-cost production of truly unique individual chips in volume manufacturing, compatible with optical systems. Mapper Lithography has introduced the FLX-1200 platform installed at CEA-Leti. This paper will present fully process-integration stepwise developments to be compliant with the single via layer demanding targets based on dual damascene process:

The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach:

- 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV

- 2/ Litho/etch process of product wafer with VSB 50keV

- 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV

- 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested.

Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application.
Conference Presentation
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Isabelle Servin, Patricia Pimenta-Barros, Arthur Bernadac, Jonathan Pradelles, Allan Germain, Yoann Blancquaert, Philippe Essomba, Stefan Landis, Gerard ten Berge, Marco Wieland, Philippe Brun, "Process development of a maskless N40 via level for security application with multi-beam lithography", Proc. SPIE 10584, Novel Patterning Technologies 2018, 1058411 (19 March 2018); doi: 10.1117/12.2297162; https://doi.org/10.1117/12.2297162
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