The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach:
- 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV
- 2/ Litho/etch process of product wafer with VSB 50keV
- 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV
- 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested.
Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application.