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19 March 2018 Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)
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Abstract
Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration flow (2). This in turn allows to extend the usage of existing process and metrology platforms, and reduce the cost of shifting to a new technology. Even though the integration changes seem limited, it springs many new obstacle for fab metrology. New parameters of interest take place, and the metrology capability needs to reach higher performance, and develop new solution methods (3,4). The current paper will focus on one of the new rising metrology challenges, which exist at the nanowire release process step. The nanowire release step, a SiGe dummy layer is being removed by dry etching, to leave behind the active Silicon nanowires, for nfet device. A detailed metrology of these nanowire profile and thickness is required to verify the device can perform to the expected specifications. To examine the scatterometry performance at this application, a specific design of experiment was set, at multiple process step. at fin formation we begin with split condition, on the silicon-silicon germanium (Si-SiGe) multi layer deposition, where SiGe , are being varied between wafers, by increasing the SiGe layer thickness, thus different amount of SiGe material will be released (figure 1a). Scatterometry and X-ray reflectivity (XRR) are verifying this split condition (figure 1b). We continue with additional split condition for the fin reveal, allowing the lower SiGe layer to be more or less revealed to the SiGe release etching step (figure 2a). To confirm the fin height for the different splits condition we use atomic force microscope (AFM), and scatterometry (figure 2b). the last process DoE we report is the etching method in which the SiGe is released. The two etch methods, we address in this paper, provides different nanowire profile (figure 3), a circular or rectangular shapes, respectively. The last part of this paper will highlight how scatterometry nanowire profile accuracy, at the SiGe release step, is improved by incorporating the complete GAA steps scatterometry solutions, and the combination of Transmission electron microscopy (TEM) rich sampling.
Conference Presentation
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Anne-Laure Charley, Hans Mertens, Naoto Horiguchi , Philippe Leray, Nivea Figueiró, Matthew Sendelbach, Roy Koret, Avron Ger, and Shay Wolfling "Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)", Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 1058505 (19 March 2018); https://doi.org/10.1117/12.2300972
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