22 March 2018 Line-width roughness of advanced semiconductor features by using FIB and planar-TEM as reference metrology
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Abstract
LER (Line Edge Roughness) and LWR (Line Width Roughness) of the semiconductor device are an important evaluation scale of the performance of the device. Conventionally, LER and LWR is evaluated from CD-SEM (Critical Dimension Scanning Electron Microscope) images. However, CD-SEM measurement has a problem that high frequency random noise is large, and resolution is not sufficiently high. For random noise of CD-SEM measurement, some techniques are proposed. In these methods, it is necessary to set parameters for model and processing, and it is necessary to verify the correctness of these parameters using reference metrology. We have already proposed a novel reference metrology using FIB (Focused Ion Beam) process and planar-TEM (Transmission Electron Microscope) method. In this study, we applied the proposed method to three new samples such as SAQP (Self-Aligned Quadruple Patterning) FinFET device, EUV (Extreme Ultraviolet Lithography) conventional resist, and EUV new material resist. LWR and PSD (Power Spectral Density) of LWR are calculated from the edge positions on planar-TEM images. We confirmed that LWR and PSD of LWR can be measured with high accuracy and evaluated the difference by the proposed method. Furthermore, from comparisons with PSD of the same sample by CD-SEM, the validity of measurement of PSD and LWR by CD-SEM can be verified.
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Kiyoshi Takamasu, Kiyoshi Takamasu, Satoru Takahashi, Satoru Takahashi, Hiroki Kawada, Hiroki Kawada, Masami Ikota, Masami Ikota, } "Line-width roughness of advanced semiconductor features by using FIB and planar-TEM as reference metrology", Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 105850E (22 March 2018); doi: 10.1117/12.2296463; https://doi.org/10.1117/12.2296463
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