16 March 2018 Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement
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The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David Jayez, David Jayez, Kevin Jock, Kevin Jock, Yue Zhou, Yue Zhou, Venugopal Govindarajulu, Venugopal Govindarajulu, Zhen Zhang, Zhen Zhang, Fatima Anis, Fatima Anis, Felipe Tijiwa-Birk, Felipe Tijiwa-Birk, Shivam Agarwal, Shivam Agarwal, } "Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement", Proc. SPIE 10585, Metrology, Inspection, and Process Control for Microlithography XXXII, 105851B (16 March 2018); doi: 10.1117/12.2302973; https://doi.org/10.1117/12.2302973

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