20 March 2018 Improving 130nm node patterning using inverse lithography techniques for an analog process
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Abstract
Developing a new lithographic process routinely involves usage of lithographic toolsets and much engineering time to perform data analysis. Process transfers between fabs occur quite often. One of the key assumptions made is that lithographic settings are equivalent from one fab to another and that the transfer is fluid. In some cases, that is far from the truth. Differences in tools can change the proximity effect seen in low k1 imaging processes. If you use model based optical proximity correction (MBOPC), then a model built in one fab will not work under the same conditions at another fab. This results in many wafers being patterned to try and match a baseline response. Even if matching is achieved, there is no guarantee that optimal lithographic responses are met. In this paper, we discuss the approach used to transfer and develop new lithographic processes and define MBOPC builds for the new lithographic process in Fab B which was transferred from a similar lithographic process in Fab A. By using PROLITHTM simulations to match OPC models for each level, minimal downtime in wafer processing was observed. Source Mask Optimization (SMO) was also used to optimize lithographic processes using novel inverse lithography techniques (ILT) to simultaneously optimize mask bias, depth of focus (DOF), exposure latitude (EL) and mask error enhancement factor (MEEF) for critical designs for each level.
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Can Duan, Can Duan, Scott Jessen, Scott Jessen, David Ziger, David Ziger, Mizuki Watanabe, Mizuki Watanabe, Steve Prins, Steve Prins, Chi-Chien Ho, Chi-Chien Ho, Jing Shu, Jing Shu, } "Improving 130nm node patterning using inverse lithography techniques for an analog process", Proc. SPIE 10587, Optical Microlithography XXXI, 1058718 (20 March 2018); doi: 10.1117/12.2297219; https://doi.org/10.1117/12.2297219
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