This PDF file contains the front matter associated with SPIE Proceedings Volume 10588, including the Title Page, Copyright information, Table of Contents, introduction (if any), and Conference Committee listing.

In imec predictive N5 technology platform (poly pitch 42nm, metal pitch 32nm), enabling cell height reduction from 6 to 5 tracks constitutes an interesting opportunity to reduce area of digital IP-blocks without increasing wafer cost. From a physical point of view, the two main challenges of reducing the number of tracks are posed by the increased difficulty of completing inter-cell connections in standard cell design, and by increased pin density that makes more challenging for the router to maintain high placement densities. Both these issues can potentially result into cell and chip area enlargement, thus mitigating or canceling the benefits of moving to 5-Tracks. In this study this side effect was avoided through a careful Design-Technology Co-Optimization approach (DTCO) [1], where a set of design arcs was used in conjunction with an EUV compatible ruleset that allowed efficient 5-Tracks standard cell design, resulting in final area gains up to 17% that were validated through a commercial state-of-the-art Place and Route (P&R) flow.

As advanced semiconductor technologies continue to shrink, there is a continued need for interconnect performance and variability to keep pace. Traditional area scaling alone cannot control the increased process variation at advanced nodes. We examine the impact that patterning scheme has on the final interconnect resistance, capacitance and RC variability at sub-36nm pitches. Industry standard patterning schemes are evaluated using the Monte Carlo method. Single exposure (direct print), litho-etch-litho-etch, self-aligned double patterning and self-aligned quadruple patterning (SAQP) are considered. In the context of these patterning schemes, lithographic variation and spacer thickness uniformity (where applicable) are evaluated.

Building on previous work for cataloging unique topological patterns in an integrated circuit physical design, a new process is defined in which a risk scoring methodology is used to rank patterns based on manufacturing risk. Patterns with high risk are then mapped to functionally equivalent patterns with lower risk. The higher risk patterns are then replaced in the design with their lower risk equivalents. The pattern selection and replacement is fully automated and suitable for use for full-chip designs. Results from 14nm product designs show that the approach can identify and replace risk patterns with quantifiable positive impact on the risk score distribution after replacement.

The ever increasing pattern densities and design complexities make the tuning of optical proximity correction (OPC) recipes very challenging. One known method for tuning is genetic algorithm (GA). Previously GA has been demonstrated to fine tune OPC recipes in order to achieve better results for possible 1D and 2D geometric concerns like bridging and pinching. This method, however, did not take into account the impact of excess segmentation on downstream operations like fracturing and mask writing.

This paper introduces a general methodology to significantly reduce the number of excess edges in the OPC output, thus reducing the number of flashes generated at fracture and subsequently the write time at mask build. GA is used to reduce the degree of unwarranted segmentation while ensuring good OPC quality. An Objective Function (OF) is utilized to ensure quality convergence and process-variation (PV) plus an additional weighed factor to reduce clustered edge count.

The technique is applied to 14nm metal layer OPC recipes in order to identify excess segmentation and to produce a modified recipe that significantly reduces these segments. OPC output file sizes is shown to be reduced by 15% or more and overall edge count is shown to be reduced by 10% or more. At the same time overall quality of the OPC recipe is shown to be maintained via OPC Verification (OPCV) results.

In this paper the bias table models and rules-based correction strategies for the wafer scale nanoimprint lithography (NIL) technology are addressed using complete Scanning Electron Microscopy (SEM) characterizations. This replication technology is known to induce Critical Dimension (CD) variations between the master and the imprint, due to polymer shrinkage, soft stamp deformation or thermal expansion. The bias between the former and final object follows peculiar rules which are specific to this process. To emphasis these singularities, Critical Dimension (CD) uniformity analyses are performed onto 200 mm wafers imprinted with the HERCULES® NIL equipment platform. Dedicated masters were manufactured which have horizontal and vertical line arrays, with local densities ranging from 0.1 to 0.9, with a minimum CD of 250 nm. The silicon masters were manufactured with 248 optical lithography and dry etching and treated with an anti-sticking layer from Arkema. CD measurements were made for the master and the replicates on 48 well selected features to build an interpolation. The data revealed that the CD evolutions can be modelled by polynomial functions with respect to the density, the CD and the orientation (vertical or horizontal) on the GDS. Finally the focus is made on the dependence of the design rules with respect to the position on the master, and it opens the discussion on the strategies for efficient wafer scale corrections for the nanoimprint soft stamp technologies.

This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two architectures examined in this paper differ primarily in their use of different power-distribution-networks to achieve the desired circuit performance for high-performance logic designs. The paper shows the importance of incorporating block-level routability experiments in the early phases of design-technology co-optimization by reviewing a series of routing trials that explore different aspects of the technology definition. Since the electrical and physical parameters leading to critical process assumptions and design rules are unique to specific integration schemes and design objectives, it is understood that the goal of this work is not to promote one cell-architecture over another, but rather to convey the importance of exploring critical trade-offs long before the process details of the technology node are finalized to a point where a process design kit can be published.

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.

Standard cell track height scaling has been identified as an option to provide significant area savings. A direct consequence of track height reduction is that the width of the power rails needs to be reduced to accommodate patterning constraints as well as leave sufficient tracks for routing. Narrower power rails are highly resistive, reducing the headroom near an operating cell due to IR drop, which is not acceptable. For example, a 20% performance loss is observed due to a 10% supply voltage drop. To worsen the situation of IR drop, a slowdown in CPP scaling and newer metallization options are making the power rail highly sensitive and its design choice is a widely debated topic in the industry. Therefore, we propose an approach to define the power rail specifications and some feasible technology solutions to solve the power grid bottleneck.

A pattern matching and rule-based polygon clustering methodology with DFM scoring is proposed to detect decomposition-induced manufacturability detractors and fix the layout designs prior to manufacturing. A pattern matcher scans the layout for pre-characterized patterns from a library. If a pattern were detected, rule-based clustering identifies the neighboring polygons that interact with those captured by the pattern. Then, DFM scores are computed for the possible layout fixes: the fix with the best score is applied. The proposed methodology was applied to two 20nm products with a chip area of 11 mm² on the metal 2 layer. All the hotspots were resolved. The number of DFM spacing violations decreased by 7-15%.

At advanced process nodes, especially at sub-28nm technology, pin accessibility and routability of standard cells has become one of the most challenging design issues due to the limited router tracks and the increased pin density. If this issue can’t be found and resolved during the cell design stage, the pin access problem will be very difficult to be fixed in implementation stage and will make the low efficiency for routing.

In this paper, we will introduce a holistic approach for the pin accessibility scoring and routability analysis. For accessibility, the systematic calculator which assigns score for each pin will search the available access points, consider the surrounded router layers, basic design rule and allowed via geometry. Based on the score, the “bad” pins can be found and modified. On pin routability analysis, critical pin points (placing via on this point would lead to failed via insertion) will be searched out for either layout optimization guide or set as OBS for via insertion blocking. By using this pin routability and pin access analysis flow, we are able to improve the library quality and performance.

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit’s mismatch. To overcome the problem and improve the turn-around time, we proposed our smart “anchoring” placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.

Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.

The design and optimization of highly nonlinear and complex processes like plasma etching is challenging and timeconsuming. Significant effort has been devoted to creating plasma profile simulators to facilitate the development of etch recipes. Nevertheless, these simulators are often difficult to use in practice due to the large number of unknown parameters in the plasma discharge and surface kinetics of the etch material, the dependency of the etch rate on the evolving front profile, and the disparate length scales of the system. Here, we expand on the development of a previously published, data informed, Bayesian approach embodied in the platform RODEo (Recipe Optimization for Deposition and Etching). RODEo is used to predict etch rates and etch profiles over a range of powers, pressures, gas flow rates, and gas mixing ratios of an CF4/Ar gas chemistry. Three examples are shown: (1) etch rate predictions of an unknown material “X” using simulated experiments for a CF₄/Ar chemistry, (2) etch rate predictions of SiO₂ in a Plasma-Therm 790 RIE reactor for a CF₄/Ar chemistry, and (3) profile prediction using level set methods.

In recent years, various methods for hotspot detection during optical proximity correction (OPC) verification have been studied. They try to predict hotspots by analyzing optical features of aerial image such as peak intensity. However, detection accuracy in these conventional methods is still not sufficient. We cannot distinguish hotspots from nonhotspots by only focusing on aerial image of hotspot because one often becomes hotspot and the other does not despite of the same aerial images. On the other hand, optical features of pattern next to the hotspot are different even in such a case. Therefore, optical features which are extracted from surrounding patterns of hotspot are one of the promising metrics for hotspot detection. In this paper, we propose a new method to detect hotspots more accurately. A new metric, Surrounding Optical Feature (SOF), is introduced. SOF indicates optical features which are extracted from surrounding pattern of the evaluated pattern. The optical feature includes critical dimension (CD), normalized image log-slope (NILS), integral intensity, peak intensity of optical image. The proposed method consists of two steps. In step 1, appropriate SOF is extracted by using training data. In step 2, OPC verification is carried out with the SOF. The effectiveness of the proposed method is confirmed in the experimental comparisons.

At advanced and mainstream process nodes (e.g., 7nm, 14nm, 22nm, and 55nm process nodes), lithography hotspots can exist in layouts of integrated circuits even if the layouts pass design rule checking (DRC). Existence of lithography hotspots in a layout can cause manufacturability issues, which can result in yield losses of manufactured integrated circuits. In order to detect lithography hotspots existing in physical layouts, pattern matching (PM) algorithms and commercial PM tools have been developed. However, there are still needs to use DRC tools to perform PM operations. In this paper, we propose a PM synthesis methodology, which uses a continuous refinement technique, for the automatic synthesis of a given lithography hotspot pattern into a DRC deck, which consists of layer operation commands, so that an equivalent PM operation can be performed by executing the synthesized deck with the use of a DRC tool. Note that the proposed methodology can deal with not only exact patterns, but also range patterns. Also, lithography hotspot patterns containing multiple layers can be processed. Experimental results show that the proposed methodology can accurately and efficiently detect lithography hotspots in physical layouts.

Finding the true on-product hot spots (patterning defects) by High Volume Manufacturing (HVM) inspection tools is increasingly challenging as the process window margin shrinks. It is a common practice nowadays to use Optical Rule Check (ORC) results by computation lithography to provide “care areas” to increase the signal to noise level of the inspection tool, thus improving the detection accuracy. The care area defined by the traditional method of contour-based process window checks may not be good enough. There are cases where real yield killers were not caught by contour-based checks, resulting in missing errors during wafer inspection as well. In this paper, we expand the traditional process window checks to a broader lithographic spectrum. The method allows us to utilize additional limiters such as max intensity, contrast, and NILS checks in combination with normal CD-based checks such as bridge, pinch, or process window bands to achieve higher accuracy in failure locations. This compound check will be trained using existing on product failure data obtained from low and high resolution wafer inspection as well as eTest and yield data. The combination of contour and intensity-based checks is demonstrated to be more effective in capturing the wafer hot spots for new products. The various usage models of such enhanced ORC will also be discussed.

Advances in pattern-based layout tools enable automatic and rapid capture, tailoring, creation, classification, and comparison/matching (accurate or fuzzy) of large quantities of patterns. Applications of such tools have significantly improved traditional script- or manual- based approaches, and have produced impressive results in production OPC and mask work. In this work, we introduce into NXP mask preparation a flow with pattern-matching-assisted mask data inspection solution, employing Cadence Pattern Analysis (CPA) tool. We also engage in CPA-facilitated creation of pattern libraries to achieve more comprehensive results in more automatic ways than what could be realized with traditional approaches, and utilize these patterns to accelerate OPC tuning, monitoring, and optimization.

In order to maintain the scaling trend in logic technology node progression, imec technology nodes started heavily utilizing design technology co-optimization (DTCO) on top of loosen pitch scaling trend to mitigate the burden from steep cost increase and yield challenge. Scaling boosters are adopted to enable DTCO process on top of patterning near its cliff to mitigate the cost increase. As the technology node further proceeds, DTCO also starts facing its cliff, and system technology co-optimization (STCO) is introduced to assist pitch and DTCO scaling to bridge 2-D IC technology to evolutionary technology options such as MRAM, 2.5-D heterogeneous integration, 3-D integration and 3-D IC. EUV is used to further assist pitch and DTCO scaling to maintain low cost with higher yield and faster turn-around-time (TAT). EUV single patterning, multiple patterning and high-NA EUV are considered on top of DTCO and STCO landscape to define imec technology nodes.

Low throughput has been a critical issue in extreme ultraviolet (EUV) patterning due to the difficulty in increasing light source power. This limitation has driven the need for photoresists with better throughput which unfortunately come with higher line edge roughness (LER). In this work, the possibility of relaxing LER requirements for metal layer patterned by EUV lithography (EUVL) is studied. Single patterning and litho-etch litho-etch (LELE) patterning with EUVL are considered. To assess the impact of LER on design yield, analytical and simulation based modeling approaches are developed, which consider the LER induced metal wire shorts/opens and the enhanced time dependent dielectrics breakdown (TDDB) for metal wires with different geometries. The impact of LER on wire delay is studied by Elmore’s delay model.

Self-Aligned-Multi-Pattering (SAMP) played an important role in extending Moore’s law over the past years especially in advanced technology nodes beyond 20nm. SAMP was tackled using several approaches, the main and most commonly used approaches are SADP with Spacer-Is-Mask (SIM) and SADP with Spacer-Is-Dielectric (SID). The first approach SADP-SIM is most commonly used in devices layer with unidirectional lines. The second approach SADP-SID is now a common approach applied in metal layers with thigh pitches especially in 7nm and 5nm technologies where the original target patterns are decomposed into a Mandrel mask and Cut Mask. The Mandrel mask is printed first using DUV 193i lithography process, then side walls are grown on both sides of the printed Mandrel patterns, and then a Cut/Block mask is printed to define target’s intended tip-to-tip spacing. The summation of side walls and Cut/Blocks act as an etchblocking layer to the regions they are covering, in another words, trenches are grown in all areas that are not covered by side walls nor cut/blocks. A complementary process for SADP-SID is the filling process, where unidirectional design, consists of aligned target patterns, are accommodated into aligned tracks. The aligned tracks are alternately assigned as Mandrel and non-Mandrels tracks. The Cut/Block defines a gap within the target and accordingly define target’s tip-totip spacing. The spacing constraints between target’s line ends and tip-to-tip spacing are translated into spacing constrains between Cut/Blocks, and based on place and route style, the density of Cut/Blocks mask is defined. Usually, in real-life designs Cut/Blocks mask density is high and comes with tight spacing constrains. The challenge with printing a cut/Blocks mask with such tight constraints and spacing rules among Cut/Blocks shapes, mandated LEn Cut/Blocks Masks with 2, 3 and sometimes 4 masks, based on how close are the cut shapes to each other. Recently, a Selective- Etching SADP-SID approach was introduced in advanced nodes, where Cut/Blocks are divided into two types, Mandrel Cut/Blocks that cut only Mandrel tracks, and non-Mandrel Cut/Blocks that cut only non-Mandrel tracks, and hence these two cut/Blocks masks can overlap each other and this significantly mitigates spacing constrains between the two Cut/Block masks.

In this work we present a comparison between manufacturing flows of traditional approach SADP-SID and Selective- Etching SADP-SID, and how can the process definition of each approach affects spacing constraints between Cut/Blocks patterns, OPC masks, and accordingly, affect the final manufactured patterns quality quantified based on Edge- Placement-Error (EPE) and Process Variation Band (PVBand).

Printing cut mask in SAMP (Self Aligned Multi Patterning) is very challenging at advanced nodes. One of the proposed solutions is to print the cut shapes selectively. Which means the design is decomposed into mandrel tracks, Mandrel cuts and non-Mandrel cuts. The mandrel and non-Mandrel cuts are mutually independent which results in relaxing spacing constrains and as a consequence more dense metal lines. In this paper, we proposed the manufacturing flow of selective etching process. The results are quantified in terms of measuring PVBand, EPE and the number of hard bridging and pinching across the layout.

As the minimum feature size continues to shrink down, the interconnect resistance is getting more important. The wire RC delay now often limits the overall chip performance. In this paper, we address a wire width optimization in self-aligned double patterning (SADP) process, where wire widening and double via insertion are considered simultaneously to minimize the total wire delay of timing critical paths. For each of the wires on the critical paths, the candidate directions to which we enlarge the wire is identified while design rules are taken into account. Each candidate direction is then evaluated in terms of the potential wire delay reduction. We finally select an optimal widening configuration by reducing the problem into a minimum weight independent set (MWIS), which is solved by using an integer learning programming (ILP) solver. Experiments are conducted for a few test circuits; wire resistance is reduced by 22.4%, on average, which allows the clock period to be reduced by 12.5%.

Line patterning, in via first dual damascene approach, is conditioned by vias density: bottom anti–reflective coating (BARC), used to minimize thin film interference effects by reducing reflected light, and photoresist reflow into vias, leading to materials thickness variation, and so to unwanted modification of metal lines critical dimension (CD), due to local reflectivity change and to swing effect. Aim of the work is to assess CD variations to be expected at device level when applying via first integration scheme, in order to compensate them, where and when feasible, or to setup restrictions to vias density at design level, forbidding critical configurations that might lead to patterning failures. The paper presents an experimental characterization of metal line CD variation as a function of vias density based on the study of a test pattern, designed to explore a wide variety of vias and metals respective configurations, and investigates different approaches to model and predict CD deviations from expected targets. Vias densities, or their convolution with specific kernels, are extracted using conventional design rule check (DRC) tools, and are used as predictors to model metal lines CD variation behavior. Simple via density computation is not able to capture the effect, so we propose a flow, based on machine learning artificial neural network algorithms, able to predict metal line width variations to be expected on product devices as a function of the vias pattern underneath.

Sub-resolution assist features (SRAFs) have become an integral part of low-k lithography’s resolution enhancement techniques (RET). Gradually maturing EUV technology indicates that SRAF insertion might be necessary for 5nm technology nodes and below.

In mask synthesis flows, during the correction step, an SRAF print avoidance (SPA) algorithm is relying on detection of printing predicted by model based simulation. In this paper we are presenting a cross-MEEF based SPA approach that offers elimination of SRAF printing while minimizing impact on process window.

As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become a big source of yield detractors. Thus tuning lithographic recipes to cover a big range of litho hotspots is very essential to yield enhancing. During early technology developing stage, foundries only have limited customer layout data for recipe tuning. So collecting enough patterns is significant for process optimization. After accumulating enough patterns, a general way to treat them is not precise and applicable. Instead, an approach to scoring these patterns could provide a priority and reference to address different patterns more effectively. For example, the weakest group of patterns could be applied the most limited specs to ensure process robustness. This paper presents a new method of creation of real design alike patterns of multiple layers based on design rules using Layout Schema Generator (LSG) utility and a pattern scoring flow using Litho-friendly Design (LFD) and Pattern Matching. Through LSG, plenty of new unknown patterns could be created for further exploration. Then, litho simulation through LFD and topological matches by using Pattern Matching is applied on the output patterns of LSG. Finally, lithographical severity, printability properties and topological distribution of every pattern are collected. After a statistical analysis of pattern data, every pattern is given a relative score representing the pattern’s yield detracting level. By sorting the output pattern score tables, weak patterns could be filtered out for further research and process tuning. This pattern generation and scoring flow is demonstrated on 28nm logic technology node. A weak pattern library is created and scored to help improve recipe coverage of litho hotspots and enhance the reliability of process.

The goal of a foundry partner is to deliver high quality silicon product to its customers on time. There is an assumed trust that the silicon will yield, function and perform as expected when the design fits all the sign-off criteria. The use of Intellectual Property (IP) blocks is very common today and provides the customer with pre-qualified and optimized functions for their design thus shortening the design cycle. There are many methods by which an IP Block can be generated and placed within layout. Even with the most careful methods and following of guidelines comes the responsibility of sign-off checking. A foundry needs to detect where these IP Blocks have been placed and look for any violations. This includes DRC clean modifications to the IP Block which may or may not be intentional.

Using a pattern-based approach to detect all IP Blocks used provides the foundry advanced capabilities to analyze them further for any kind of changes which could void the OPC and process window optimizations. Having any changes in an IP Block could cause functionality changes or even failures. This also opens the foundry to legal and cost issues while at the same time forcing re-spins of the design.

In this publication, we discuss the methodology we have employed to avoid process issues and tape-out errors while at the same time reduce our manual work and improve the turnaround time. We are also able to use our pattern analysis to improve our OPC optimizations when modifications are encountered which have not been seen before.

As integrated circuits (IC) technology moves forward, manufacturing process is facing more and more challenges. Optical proximity correction (OPC) has been playing an important role in the whole manufacturing process. In the deep sub-micron technology, OPC engineers not only need to guarantee the layout designs to be manufacturable but also take a more precise control of the critical patterns to ensure a high performance circuit. One of the tasks that would like to be performed is the consistency checking as the identical patterns under identical context should have identical OPC results in theory, like SRAM regions. Consistency checking is essentially a technique of repeated patterns identification, extraction and derived patterns (i.e. OPC results) comparison. The layout passing to the OPC team may not have enough design hierarchical information either because the original designs may have undergone several layout processing steps or some other unknown reasons. This paper presents a generic way to identify and extract repeated layout structures in SRAM regions purely based on layout pattern analysis through Calibre Pattern Matching and Calibre equation-based DRC (eqDRC). Without Pattern Matching and eqDRC, it will take lots of effort to manually get it done by trial and error, it is almost impossible to automate the pattern analysis process. Combining Pattern Matching and eqDRC opens a new way to implement this flow. The repeated patterns must have some fundamental features for measurement of pitches in the horizontal and vertical direction separately by Calibre eqDRC and meanwhile can be a helper to generate some anchor points which will be the starting points for Pattern Matching to capture patterns. The informative statistical report from the pattern search tells the match counts individually for each patterns captured. Experiment shows that this is a smart way of identifying and extracting repeated structures effectively. The OPC results are the derived layers on these repeated structures, by running pattern search using design layers as pattern layers and OPC results as marker layers, it is an easy job to compare the consistency.

A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis.

This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.

As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.

Memory is a critical component in today's system-on-chip (SoC) designs. Static random-access memory (SRAM) blocks are assembled by combining intellectual property (IP) blocks that come from SRAM libraries developed and certified by the foundries for both functionality and a specific process node. Customers place these SRAM IP in their designs, adjusting as necessary to achieve DRC-clean results. However, any changes a customer makes to these SRAM IP during implementation, whether intentionally or in error, can impact yield and functionality. Physical verification of SRAM has always been a challenge, because these blocks usually contain smaller feature sizes and spacing constraints compared to traditional logic or other layout structures. At advanced nodes, critical dimension becomes smaller and smaller, until there is almost no opportunity to use optical proximity correction (OPC) and lithography to adjust the manufacturing process to mitigate the effects of any changes. The smaller process geometries, reduced supply voltages, increasing process variation, and manufacturing uncertainty mean accurate SRAM physical verification results are not only reaching new levels of difficulty, but also new levels of criticality for design success. In this paper, we explore the use of pattern matching to create an SRAM verification flow that provides both accurate, comprehensive coverage of the required checks and visual output to enable faster, more accurate error debugging. Our results indicate that pattern matching can enable foundries to improve SRAM manufacturing yield, while allowing designers to benefit from SRAM verification kits that can shorten the time to market.

Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation.

PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.

As the semiconductor industry enters 20 nm node and beyond, design restrictions and process complexity lay stress on the development for a new technology node. This paper introduces a hybrid hotspot library building method based on simultaneous optical and geometry analysis, which could help explore design rule optimization and enhance cycle time at early stage for new node development. Lithography simulation results verify the accuracy of this method. This method provide a feasible way to build up a preliminary Design Rule Checking (DRC) library even before process-freezing.