PROCEEDINGS VOLUME 10588
SPIE ADVANCED LITHOGRAPHY | 25 FEBRUARY - 1 MARCH 2018
Design-Process-Technology Co-optimization for Manufacturability XII
Editor(s): Jason P. Cain
Proceedings Volume 10588 is from: Logo
SPIE ADVANCED LITHOGRAPHY
25 February - 1 March 2018
San Jose, California, United States
Trends in DPTCO
Proc. SPIE 10588, Efficient place and route enablement of 5-tracks standard-cells through EUV compatible N5 ruleset, 1058803 (20 March 2018); doi: 10.1117/12.2297336
Proc. SPIE 10588, Patterning method impact on sub-36nm pitch interconnect variability, 1058804 (20 March 2018); doi: 10.1117/12.2297117
Proc. SPIE 10588, Applying machine learning to pattern analysis for automated in-design layout optimization , 1058805 (10 April 2018); doi: 10.1117/12.2299492
Pattern Correction Methods: Joint session with conferences 10588 and 10587
Proc. SPIE 10588, Optimization of optical proximity correction to reduce mask write time using genetic algorithm, 1058806 (20 March 2018); doi: 10.1117/12.2297400
Proc. SPIE 10588, Dependencies of bias tables to pattern density, critical dimension, global coordinates and pattern orientation for nanoimprint master manufacturing for the 200 mm wafer scale SmartNIL process, 1058807 (20 March 2018); doi: 10.1117/12.2299326
Design-Technology Co-optimization
Proc. SPIE 10588, pre-pdk block-level ppac assessment of technology options for sub-7nm high-performance logic, 1058808 (20 March 2018); doi: 10.1117/12.2297634
Proc. SPIE 10588, Track height reduction for standard-cell in below 5nm node: How low can you go?, 1058809 (20 March 2018); doi: 10.1117/12.2297191
Proc. SPIE 10588, A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing, 105880A (20 March 2018); doi: 10.1117/12.2297519
Proc. SPIE 10588, DTCO exploration for efficient standard cell power rails, 105880B (20 March 2018); doi: 10.1117/12.2293500
Layout Optimization
Proc. SPIE 10588, Post-decomposition optimizations using pattern matching and rule-based clustering for multi-patterning technology, 105880C (20 March 2018); doi: 10.1117/12.2297508
Proc. SPIE 10588, Pin routability and pin access analysis on standard cells for layout optimization, 105880D (20 March 2018); doi: 10.1117/12.2297290
Proc. SPIE 10588, Variability-aware double-patterning layout optimisation for analog circuits, 105880E (20 March 2018); doi: 10.1117/12.2297159
Proc. SPIE 10588, Litho friendly via insertion with in-design auto-fix flow using machine learning, 105880F (4 April 2018); doi: 10.1117/12.2297499
Design Interactions: Joint session with conferences 10585 and 10588
Proc. SPIE 10588, A model-based, Bayesian approach to the CF4/Ar etch of SiO2, 105880G (20 March 2018); doi: 10.1117/12.2297482
Pattern-based Analysis
Proc. SPIE 10588, Hotspot detection based on surrounding optical feature, 105880I (20 March 2018); doi: 10.1117/12.2297189
Proc. SPIE 10588, range pattern matching with layer operations and continuous refinements, 105880J (20 March 2018); doi: 10.1117/12.2297351
Proc. SPIE 10588, Combinational optical rule check on hotspot detection (Conference Presentation), 105880K (28 March 2018); doi: 10.1117/12.2297425
Proc. SPIE 10588, Pattern analysis and classification accelerates OPC tuning, monitoring, and optimization and mask inspection, 105880L (20 March 2018); doi: 10.1117/12.2297097
Advanced Patterning
Proc. SPIE 10588, IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend, 105880N (20 March 2018); doi: 10.1117/12.2299335
Proc. SPIE 10588, Relaxing LER requirements in EUV patterning, 105880O (20 March 2018); doi: 10.1117/12.2297515
Proc. SPIE 10588, Comparison between multi-colored LEn SADP/SAQP and selective-etching SADP/SAQP, 105880P (20 March 2018); doi: 10.1117/12.2297417
Proc. SPIE 10588, Integrated manufacturing flow for selective-etching SADP/SAQP, 105880Q (20 March 2018); doi: 10.1117/12.2297415
Poster Session
Proc. SPIE 10588, Timing optimization in SADP process through wire widening and double via insertion, 105880R (20 March 2018); doi: 10.1117/12.2297496
Proc. SPIE 10588, Characterization of metal line-width variation in via first dual-damascene approach and its modeling using machine learning artificial neural network algorithms, 105880S (20 March 2018); doi: 10.1117/12.2297256
Proc. SPIE 10588, Cross-MEEF assisted SRAF print avoidance approach, 105880T (20 March 2018); doi: 10.1117/12.2297227
Proc. SPIE 10588, A weak pattern random creation method for lithography process tuning, 105880U (20 March 2018); doi: 10.1117/12.2297296
Proc. SPIE 10588, pattern-based IP block detection, verification, and variability analysis, 105880V (20 March 2018); doi: 10.1117/12.2297675
Proc. SPIE 10588, A smart way to identify and extract repeated structures of a layout, 105880W (20 March 2018); doi: 10.1117/12.2297303
Proc. SPIE 10588, Using pattern based layout comparison for a quick analysis of design changes, 105880X (20 March 2018); doi: 10.1117/12.2297346
Proc. SPIE 10588, An efficient way of layout processing based on pattern matching and DRC for defects inspection application, 105880Y (20 March 2018); doi: 10.1117/12.2297349
Proc. SPIE 10588, Leveraging pattern matching to solve SRAM verification challenges at advanced nodes, 105880Z (20 March 2018); doi: 10.1117/12.2297340
Proc. SPIE 10588, A portable pattern-based design technology co-optimization flow to reduce optical proximity correction run-time, 1058810 (20 March 2018); doi: 10.1117/12.2297077
Proc. SPIE 10588, Hybrid hotspot library building based on optical and geometry analysis at early stage for new node development, 1058811 (20 March 2018); doi: 10.1117/12.2296834
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