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20 March 2018 Variability-aware double-patterning layout optimization for analog circuits
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The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double-patterning lithography layout masks, two polygons are assigned to different masks if their spacing is less than the minimum printable spacing. With these additional design constraints, it is very difficult to find experienced layout-design engineers who have a good understanding of the circuit to manually optimize the mask layers in order to minimize color-induced circuit variations. In this work, we investigate the impact of double-patterning lithography on analog circuits and provide quantitative analysis for our designers to select the optimal mask to minimize the circuit’s mismatch. To overcome the problem and improve the turn-around time, we proposed our smart “anchoring” placement technique to optimize mask decomposition for analog circuits. We have developed a software prototype that is capable of providing anchoring markers in the layout, allowing industry standard tools to perform automated color decomposition process.
Conference Presentation
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, I-Lun Tseng, and Jonathan Yoong Seang Ong "Variability-aware double-patterning layout optimization for analog circuits", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880E (20 March 2018);

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