Pattern-based IP block detection, verification, and variability analysis

Muhamad Asraf Bin Ahmad Ibrahim; Mohamad Fahmi Bin Muhsain; Ezni Aznida Binti Kamal Baharin; Jason Sweis; Ya-Chieh Lai; Philippe Hurat

doi:10.1117/12.2297675

20 March 2018 Pattern-based IP block detection, verification, and variability analysis

Muhamad Asraf Bin Ahmad Ibrahim, Mohamad Fahmi Bin Muhsain, Ezni Aznida Binti Kamal Baharin, Jason Sweis, Ya-Chieh Lai, Philippe Hurat

Author Affiliations +

Proceedings Volume 10588, Design-Process-Technology Co-optimization for Manufacturability XII; 105880V (2018) https://doi.org/10.1117/12.2297675
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

The goal of a foundry partner is to deliver high quality silicon product to its customers on time. There is an assumed trust that the silicon will yield, function and perform as expected when the design fits all the sign-off criteria. The use of Intellectual Property (IP) blocks is very common today and provides the customer with pre-qualified and optimized functions for their design thus shortening the design cycle. There are many methods by which an IP Block can be generated and placed within layout. Even with the most careful methods and following of guidelines comes the responsibility of sign-off checking. A foundry needs to detect where these IP Blocks have been placed and look for any violations. This includes DRC clean modifications to the IP Block which may or may not be intentional.

Using a pattern-based approach to detect all IP Blocks used provides the foundry advanced capabilities to analyze them further for any kind of changes which could void the OPC and process window optimizations. Having any changes in an IP Block could cause functionality changes or even failures. This also opens the foundry to legal and cost issues while at the same time forcing re-spins of the design.

In this publication, we discuss the methodology we have employed to avoid process issues and tape-out errors while at the same time reduce our manual work and improve the turnaround time. We are also able to use our pattern analysis to improve our OPC optimizations when modifications are encountered which have not been seen before.

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Muhamad Asraf Bin Ahmad Ibrahim, Mohamad Fahmi Bin Muhsain, Ezni Aznida Binti Kamal Baharin, Jason Sweis, Ya-Chieh Lai, and Philippe Hurat "Pattern-based IP block detection, verification, and variability analysis", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880V (20 March 2018); https://doi.org/10.1117/12.2297675

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KEYWORDS

Optical proximity correction

Databases

Silicon

System on a chip

Tolerancing

Error analysis

Integrated circuit design

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