This paper discusses the process challenges and limitations for 3D NAND processes, focusing on vertical 3D architectures. The effect of deep memory hole etches on die cost is calculated, with die cost showing a minimum at a given number of layers because of aspect-ratio dependent etch effects. Techniques to mitigate these etch effects are summarized, as are other etch issues, such as bowing and twisting. Metal replacement gate processes and their challenges are also described. Lastly, future directions of vertical 3D NAND technologies are explored.