Wafer edge overlay control solution for N7 and beyond

Richard van Haren; Victor Calado; Leon van Dijk; Jan Hermans; Kaushik Kumar; Fumiko Yamashita

doi:10.1117/12.2303521

20 March 2018 Wafer edge overlay control solution for N7 and beyond

Richard van Haren, Victor Calado, Leon van Dijk, Jan Hermans, Kaushik Kumar, Fumiko Yamashita

Proceedings Volume 10589, Advanced Etch Technology for Nanopatterning VII; 105890D (2018) https://doi.org/10.1117/12.2303521
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region.

In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements.

Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Citation Download Citation

Richard van Haren, Victor Calado, Leon van Dijk, Jan Hermans, Kaushik Kumar, and Fumiko Yamashita "Wafer edge overlay control solution for N7 and beyond", Proc. SPIE 10589, Advanced Etch Technology for Nanopatterning VII, 105890D (20 March 2018); https://doi.org/10.1117/12.2303521

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