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20 March 2018 Cost modeling 22nm pitch patterning approaches
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No single lithography technology can create <24nm pitch patterns in a single pass except for direct-write e-beam which is too slow and expensive for HVM. Various complex multi-patterning process flows can be compared by Cost Per Wafer Pass (CPWP), a term defined as the cost-of-ownership (CoO) with all yield losses set to zero in high volume manufacturing (HVM). CPWP modeling allows for the evaluation of alternate 1D and 2D patterning paths, including EUV LE2, EUV SADP, ArFi LE4, ArFi SAQP + EUV cut-mask, and ArFi SADP + DSA + ArFi block-mask. Similar CPWP for ArFi- and EUV-based flows favor the latter due to reduced yield losses and manufacturing times.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Ed Korczynski "Cost modeling 22nm pitch patterning approaches", Proc. SPIE 10589, Advanced Etch Technology for Nanopatterning VII, 105890R (20 March 2018);

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