6 March 2018 Hardware-efficient implementation of digital FIR filter using fast first-order moment algorithm
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Proceedings Volume 10610, MIPPR 2017: Parallel Processing of Images and Optimization Techniques; and Medical Imaging; 1061004 (2018) https://doi.org/10.1117/12.2284452
Event: Tenth International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR2017), 2017, Xiangyang, China
Abstract
As the digital finite impulse response (FIR) filter can be transformed into the shift-add form of multiple small-sized firstorder moments, based on the existing fast first-order moment algorithm, this paper presents a novel multiplier-less structure to calculate any number of sequential filtering results in parallel. The theoretical analysis on its hardware and time-complexities reveals that by appropriately setting the degree of parallelism and the decomposition factor of a fixed word width, the proposed structure may achieve better area-time efficiency than the existing two-dimensional (2-D) memoryless-based filter. To evaluate the performance concretely, the proposed designs for different taps along with the existing 2-D memoryless-based filters, are synthesized by Synopsys Design Compiler with 0.18-μm SMIC library. The comparisons show that the proposed design has less area-time complexity and power consumption when the number of filter taps is larger than 48.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Li Cao, Jianguo Liu, Jun Xiong, Jing Zhang, "Hardware-efficient implementation of digital FIR filter using fast first-order moment algorithm", Proc. SPIE 10610, MIPPR 2017: Parallel Processing of Images and Optimization Techniques; and Medical Imaging, 1061004 (6 March 2018); doi: 10.1117/12.2284452; https://doi.org/10.1117/12.2284452
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