10 April 2018 An acceleration system for Laplacian image fusion based on SoC
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Proceedings Volume 10615, Ninth International Conference on Graphic and Image Processing (ICGIP 2017); 1061537 (2018) https://doi.org/10.1117/12.2303486
Event: Ninth International Conference on Graphic and Image Processing, 2017, Qingdao, China
Abstract
Based on the analysis of Laplacian image fusion algorithm, this paper proposes a partial pipelining and modular processing architecture, and a SoC based acceleration system is implemented accordingly. Full pipelining method is used for the design of each module, and modules in series form the partial pipelining with unified data formation, which is easy for management and reuse. Integrated with ARM processor, DMA and embedded bare-mental program, this system achieves 4 layers of Laplacian pyramid on the Zynq-7000 board. Experiments show that, with small resources consumption, a couple of 256×256 images can be fused within 1ms, maintaining a fine fusion effect at the same time.
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Liwen Gao, Hongtu Zhao, Xiujie Qu, Tianbo Wei, Peng Du, "An acceleration system for Laplacian image fusion based on SoC", Proc. SPIE 10615, Ninth International Conference on Graphic and Image Processing (ICGIP 2017), 1061537 (10 April 2018); doi: 10.1117/12.2303486; https://doi.org/10.1117/12.2303486
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