DRS has designed a full HD (1920x1080) readout integrated circuit (ROIC) specifically for cost-effective waferscale infrared (WIRED) detectors on 3 μm pitch, for best theoretical image quality optical system performance. The sensor’s pixels use a capacitive trans-impedance amplifier (CTIA) and a metal-insulator-metal (MIM) integration capacitor, to achieve 22 Ke- well capacity, 0.7 V output swing and 37 e- or 18 e- equivalent readout noise, operating at 60 Hz ripple readout mode or 30 Hz correlated double sampling (CDS) mode, respectively. The fully digital ROIC consumes approximately 0.5 W of power, allowing it to be fielded in battery-powered applications.
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A. Bakulin, A. I. D'Souza, C. Masterjohn, E. Mei, C. Li, E. Klem, D. Temple, "ROIC for 3 um Pixel Pitch Colloidal Quantum Dot Detectors ," Proc. SPIE 10656, Image Sensing Technologies: Materials, Devices, Systems, and Applications V, 1065614 (14 May 2018);