14 May 2018 Time-gated CMOS SPAD array in 0.16 μm BCD with shared timing electronics and background light rejection for LIDAR applications
Author Affiliations +
We present the design and preliminary characterization of a 32 × 32 SPAD time-gated imager in a 0.16 μm BCD technology featuring an innovative pixel structure, composed of four single-photon detectors, independent event counters and a shared Time-to-Digital Converter (TDC). This approach allows our design to reach higher fill factor (9.6 % with a pixel pitch of 100 μm) than typical SPAD imagers with in-pixel TDC, as well as reducing the power dissipation of the chip itself. The imager targets primarily LIDAR applications, but can also be employed in scientific and biomedical applications, and also features a photon-coincidence operation mode intended for rejection of background light. The developed imager performs simultaneous photon-counting and photon-timing operation and implements a 12 bit, 75 ps LSB flash-type TDC, able to perform one conversion per each gate window and up to 62 gates per acquisition frame (100 kfps maximum frame rate). The TDC structure is finely tunable, allowing to compensate for process variations and mismatches. Different readout modes allow to fit the requirements of different applications, trading-off the amount of provided data (e.g., only counting, only timing, both timing and counting) and the achievable frame rate. The readout scheme allows for easy tiling into large imagers and avoids the readout speed bottleneck typically found in standard row select / column select approaches.
Conference Presentation
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Davide Portaluppi, Davide Portaluppi, Enrico Conca, Enrico Conca, Federica Villa, Federica Villa, Franco Zappa, Franco Zappa, } "Time-gated CMOS SPAD array in 0.16 μm BCD with shared timing electronics and background light rejection for LIDAR applications", Proc. SPIE 10659, Advanced Photon Counting Techniques XII, 1065907 (14 May 2018); doi: 10.1117/12.2305035; https://doi.org/10.1117/12.2305035


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