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Adaptive Optics (AO) is a necessary technology for ensuring the success of the next generation of extremely large telescopes (ELTs). It’s used to help mitigate the perturbing effects of Earth’s atmosphere on the incoming light from astronomical objects and will be an integral part of ELTs for obtaining close to diffraction limited images. To maintain a correction of the incoming wavefront under dynamic atmospheric conditions, which can change significantly on the order of milliseconds, the frame-by-frame reconstruction must be operated in real-time, with hard limits on the time interval between measuring the disturbance and applying a correction. The main problem size for AO RTC increases with the 4th power of telescope diameter and so the computational demands of AO RTCs for ELTs, with primary mirror diameters between 20-40m, increase significantly compared to the current generation of 10m class telescopes. This makes the investigation into and the development of real-time controllers (RTCs) for ELT scale AO systems critical for ensuring the effectiveness of these instruments for first light. Green Flash, which is an ongoing EU funded project, has the aim of investigating the optimal hardware architecture for ELT scale AO RTC, with an emphasis on GPU and Xeon Phi solutions. The Intel Xeon Phi, built using Intel’s Many Integrated Core (MIC) architecture, incorporates ≥64 general purpose x86 CPU cores into a single CPU package paired with a large pool of on chip high bandwidth MCDRAM, it has many of the advantages of current technologies without some of the more significant drawbacks. The most computationally intensive aspects of most AO RTC pipelines are large matrix-vector multiplications mainly used to compute the reconstructed wavefronts which are highly parallelizable and are generally memory bandwidth bound. This makes the Xeon Phi with it’s large CPU count and high bandwidth memory ideally suited for acceleration of the reconstruction task and therefore for ELT scale AO RTC. The most recent incarnation of the Xeon Phi platform is available as a standard socketed x86 CPU allowing previous efforts made in developing CPU based RTC software to be used as a basis for a Xeon Phi based RTCs with the added advantage that any optimisations made for the MIC architecture can be carried forward to future x86 CPU based systems. The Durham Adaptive Optics Real-time Controller (DARC) is an example of a freely available, on-sky tested, fully modular, x86 CPU based AO RTC which which is ideally suited to be a basis for our investigation into ELT scale AO RTC performance. We present a proof of concept AO RTC system, in collaboration with the Green Flash project, using an optimised DARC on a multi-node homogeneous Xeon Phi cluster to demonstrate the potential of the MIC platform for AO RTC. We will present our methods of optimisation for the C based DARC for the Xeon Phi, including BIOS, kernel and OS tuning as well as considerations for multi-threading and massively parallel algorithm development.
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