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6 July 2018 Image compression on reconfigurable FPGA for the SO/PHI space instrument
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In this paper we present a novel FPGA implementation of the Consultative Committee for Space Data Systems Image Data Compression (CCSDS-IDC 122.0-B-1) for performing image compression aboard the Polarimetric Helioseismic Imager instrument of the ESA’s Solar Orbiter mission. This is a System-On-Chip solution based on a light multicore architecture combined with an efficient ad-hoc Bit Plane Encoder core. This hardware architecture performs an acceleration of ~30 times with respect to a software implementation running into space-qualified processors, like LEON3. The system stands out over other FPGA implementations because of the low resource usage, which does not use any external memory, and of its configurability.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
D. Hernández Expósito, J. P. Cobos Carrascosa, J. L. Ramos Mas, M. Rodríguez Valido, D. Orozco Suárez, J. Hirzberger, J. Woch, S. Solanki, and J. C. del Toro Iniesta "Image compression on reconfigurable FPGA for the SO/PHI space instrument", Proc. SPIE 10707, Software and Cyberinfrastructure for Astronomy V, 107072F (6 July 2018);

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