Over the last several decades, several innovative lithographic approaches have been introduced in an effort to extend device roadmaps for both memory and logic devices. For many years, the emphasis was almost strictly on resolution, with the thought that at some point, conventional reduction optical lithography would be wavelength restricted. The thought process changed around ten years ago however, with the introduction of pitch splitting techniques such as self-aligned patterning and multiple uses of litho/etch (LE) processes. For dense lines, Self-Aligned Double Patterning (SADP) methods extended resolution to about 20nm (half pitch) and was followed by quad patterning processes (SAQP) that could reduce the half pitch to 10nm. Multiple litho/etch processes have already been applied create 20nm half pitch dense contact arrays. Although these pattern multiplication processes have enabled the industry to continue to aggressively scale devices, the methods come with a cost; both technical and financial. The technical price we pay for pitch splitting comes in the way of critical dimension control and additional overlay terms (pitch walking). Despite the precision of our newest deposition and etch processes, the additional process steps used to reduce pitch introduce these types of errors. Any technology (NIL and EUVL for example) that can deliver a single litho step process has the opportunity to deliver a simplified solution with better CD and overlay control. In this work, we review the key elements that go into determining NIL CoO and compare it to existing technology. Two examples are described in detail; sub-19nm half pitch lines and dense 20nm contact arrays. The assumptions used in the model are described, and projections for further reducing CoO are discussed, based on tool throughput, mask life and other key factors.