0.6 Âµm CMOS Technology Using Desire Process

F. Vinet; M. Chevallier; J. C. Guibert; Ch. Pierrat

doi:10.1117/12.953056

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30 January 1989 0.6µm CMOS Technology Using Desire Process

F. Vinet, M. Chevallier, J. C. Guibert, Ch. Pierrat

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Proceedings Volume 1086, Advances in Resist Technology and Processing VI; (1989) https://doi.org/10.1117/12.953056
Event: 1989 Santa Clara Symposium on Microlithography, 1989, San Jose, CA, United States

Abstract

By using PLASMASK(*) resist in the DESIRE(*) process, multilayer resist performances can be achieved on a single layer. The aim of this paper is to show , for each step of DESIRE process , the influence of the different parameters on lithographic performances , and finally the use of such process on critical levels for 0.6μm CMOS technology . Exposure experiment have been performed on an I-line ASM stepper ( NA = 0.4 ) A modified HMDS vapor prime from SVG has been used for resist silylation . Silicon depth profi-les in PLASMASK resist versus dose, time and temperature of silylation have been measured by RBS method. Statistical Experimental Designs (S.E.D.) have allowed the determination of process parameters influence as well as the identification of their interactions on lithographic performances . The resulting optimized process will be demonstrated on a metal 1, 0.64μm CMOS technology. * PLASMASK and DESIRE are trademarks from UCB Electronics.

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F. Vinet, M. Chevallier, J. C. Guibert, and Ch. Pierrat "0.6µm CMOS Technology Using Desire Process", Proc. SPIE 1086, Advances in Resist Technology and Processing VI, (30 January 1989); https://doi.org/10.1117/12.953056

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