Lift-off technology provides an alternate metal patterning technology to that of subtractive etching. In this paper, we characterize a trilayer resist process which provides a practical means for producing the stencils which are required for successful lift-off in a 1.6 μm metal pitch CMOS process, with biasing for nominal mask design rule or wider metal interconnections. The trilayer structure we describe consists of a planarization layer of polydimethylglutarimide (PMGI), a spin-on organosilicon polymer intermediate layer, and a positive novolac photo-imaging layer. All three layers can be coated and cured sequentially in automated equipment, and the intermediate and planarization layers can be etched in-situ, minimizing wafer handling and contamination. The rationale for use of lifted off metal interconnections and requirements for liftoff stencils are described. In this paper, we characterize dimension biasing and proximity effects for the photoresist layer, organosilicon layer, and PMGI layer, as well as the final lifted off metal interconnections. Minimal proximity effects and differential biasing due to feature size variations are shown for feature sizes ranging from 0.7 - 2.0 μm, with biasing in favor of wider metal interconnections.