25 July 1989 Characterization Of Submicron Optical Lithography For CMOS Polysilicon Gate Electrodes
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With MOSFET technology the dominant device used in VLSI circuits, as well as the continued reduction in device dimensions, a particularly challenging lithography goal will be the patterning of submicron CMOS gate electrodes on grainy, reflective polysilicon films. This paper will provide a detailed investigation of the microlithographic optimization of such devices. Utilizing a 1:1 0.40 numerical aperture (NA) broadband lens stepper system with both high contrast mid-UV and near-UV resists, we investigated extending lithography to near resolution limit capabilities on this system by patterning CMOS gate electrodes on grainy, reflective polysilicon films for line/space dimensions of 0.8, 0.7, and 0.6 μm. Electrical test results of patterned substrates are presented to indicate the practical, ultimate resolution and process latitude of this system. The electrical results include detailed electrical data which represent the entire lithographic process including dry etch. The data was taken at 50 sites over the entire optical lens extent. Selected scanning electron micrographs of resist profiles are included to support these findings. The effects of focus and exposure variations are presented to illustrate the feasibility of implementing this system for process manufacturing in CMOS technology.
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Gary E. Flores, Gary E. Flores, Warren W. Flack, Warren W. Flack, Ronald L. Fischer, Ronald L. Fischer, Peg Videtta, Peg Videtta, } "Characterization Of Submicron Optical Lithography For CMOS Polysilicon Gate Electrodes", Proc. SPIE 1088, Optical/Laser Microlithography II, (25 July 1989); doi: 10.1117/12.953161; https://doi.org/10.1117/12.953161

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