A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon

Youcef A. Bioud; Meghan N. Beattie; Abderraouf Boucherif; Mourad Jellit; Romain Stricher; Serge Ecoffey; Gilles Patriarche; David Troadec; Ali Soltani; Nadi Braidy; Matthew Wilkins; Christopher E. Valdivia; Karin Hinzer; Dominique Drouin; Richard Arès

doi:10.1117/12.2511080

27 February 2019 A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon

Youcef A. Bioud, Meghan N. Beattie, Abderraouf Boucherif, Mourad Jellit, Romain Stricher, Serge Ecoffey, Gilles Patriarche, David Troadec, Ali Soltani, Nadi Braidy, Matthew Wilkins, Christopher E. Valdivia, Karin Hinzer, Dominique Drouin, Richard Arès

Author Affiliations +

Proceedings Volume 10913, Physics, Simulation, and Photonic Engineering of Photovoltaic Devices VIII; 109130T (2019) https://doi.org/10.1117/12.2511080
Event: SPIE OPTO, 2019, San Francisco, California, United States

Abstract

III-V solar cell cost reduction and direct III-V/Si integration can both be realized by depositing a thin layer of high-quality Ge on relatively low-cost Si substrates. However, direct epitaxial growth of Ge on Si substrates is difficult due to the 4% lattice mismatch between the film and the substrate. Threading dislocations (TDs) introduced within the Ge layer have a detrimental effect on device performances. The goal of this research is to address the perennial need to minimize the defect density of Ge epilayers grown on a Si substrate. We seek to accommodate the effects of the lattice mismatch by introducing a porous Si interface layer to intercept dislocations and prevent them from reaching the active layers of the device. The porous Si layer is formed through dislocation-selective electrochemical deep etching and thermal annealing. The porous layer created beneath the top Ge layer can both act as dislocation traps and as a soft compliant substrate, which displays high flexibility. Transmission electron microscopy (TEM) analysis of the Ge/porous Si interface shows that the lattice mismatch strain of the Ge films was almost relaxed. The surface roughness of this modified Ge/Si substrate has been reduced using chemical mechanical polishing (CMP) process to fulfil the requirements for epitaxy of III-V alloys. Finally, we present simulation results exploring the effect of threading dislocations on device performance.

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Youcef A. Bioud, Meghan N. Beattie, Abderraouf Boucherif, Mourad Jellit, Romain Stricher, Serge Ecoffey, Gilles Patriarche, David Troadec, Ali Soltani, Nadi Braidy, Matthew Wilkins, Christopher E. Valdivia, Karin Hinzer, Dominique Drouin, and Richard Arès "A porous Ge/Si interface layer for defect-free III-V multi-junction solar cells on silicon", Proc. SPIE 10913, Physics, Simulation, and Photonic Engineering of Photovoltaic Devices VIII, 109130T (27 February 2019); https://doi.org/10.1117/12.2511080

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