Alignment-tolerant interfacing of a photonic integrated circuit using back side etched silicon microlenses

J. Missinne; N. Teigell Benéitez; N. Mangal; J. Zhang; A. Vasiliev; J. Van Campenhout; B. Snyder; G. Roelkens; G. Van Steenberge

doi:10.1117/12.2506159

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4 March 2019 Alignment-tolerant interfacing of a photonic integrated circuit using back side etched silicon microlenses

J. Missinne, N. Teigell Benéitez, N. Mangal, J. Zhang, A. Vasiliev, J. Van Campenhout, B. Snyder, G. Roelkens, G. Van Steenberge

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Proceedings Volume 10923, Silicon Photonics XIV; 1092304 (2019) https://doi.org/10.1117/12.2506159
Event: SPIE OPTO, 2019, San Francisco, California, United States

Abstract

Directly interfacing a photonic integrated circuit allows at best an alignment tolerance of a few micrometer due to the small dimensions of optical (coupling) features on chip, but when using microlenses integrated on the substrate-side, alignment tolerances for interfacing the chips can greatly be relaxed. This is demonstrated on a 750 μm thick chip with standard grating couplers (operation wavelength around 1550 nm). Low roughness silicon microlenses were realized by transferring reflowed photoresist into the silicon substrate using reactive ion etching. The microlens allows interfacing the chip from the backside with an expanded beam, drastically increasing lateral alignment tolerances. A 1 dB alignment tolerance of ±8 μm and ±11 μm (along and perpendicular to the grating coupler direction, respectively) was experimentally found when a 40 μm mode field diameter beam was used at the input.

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J. Missinne, N. Teigell Benéitez, N. Mangal, J. Zhang, A. Vasiliev, J. Van Campenhout, B. Snyder, G. Roelkens, and G. Van Steenberge "Alignment-tolerant interfacing of a photonic integrated circuit using back side etched silicon microlenses", Proc. SPIE 10923, Silicon Photonics XIV, 1092304 (4 March 2019); https://doi.org/10.1117/12.2506159

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