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26 March 2019 Focus budget improvement using optimized wafer edge settings
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Abstract
To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These can be explored fully with minimum experimental effort by simulating alternative set-point curves (z; Rx; Ry) and resulting MA and MSD focus residuals from existing full wafer height maps. In this paper, optimizations are carried out to obtain the best focus edge clearance settings for several DRAM and NAND products, across different layers and exposure tools. The simulated die-fine focus errors are compared to the POR settings and verified with electrical results. Differences across products, layers, and exposure tools are discussed.
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Lucas Lamonds, Bryan Orf, Michael Frachel, Xaver Thrun, Georg Erley, Philip Groeger, Boris Habets, and Alexander Muehle "Focus budget improvement using optimized wafer edge settings", Proc. SPIE 10959, Metrology, Inspection, and Process Control for Microlithography XXXIII, 109591P (26 March 2019); https://doi.org/10.1117/12.2514978
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