While the semiconductor industry has reached the high-volume manufacturing of the 7 nm technology node (N7), patterning processes for future technology nodes N5, N3 and even below, are being investigated and developed by research centers. To achieve the critical dimensions of gratings for these future technology nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple patterning (SADP/SAQP/SAOP) and multiple litho-etch (LE) patterning, in combination with 193i lithography and even EUV lithography. These gratings need to be subsequently cut or blocked, which is typically done by one or more block masks. As the edge placement error (EPE) budget drastically decreases with decreasing critical dimensions, the standard LE block patterning scheme is not sufficient anymore. To relax the EPE budget, dedicated scaling boosters are required such as the self-aligned block scheme, which defines blocks in trenches, selectively to the neighboring trenches. In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.
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