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20 March 2019 Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level
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Abstract
The continuous scaling of 3D NAND by vertically stacking more tiers in a single die presents some major challenges . One of these challenges is the effect of increasing surface topography on photolithography. Although photolithography is relaxed in 3D NAND process compared to 2D NAND, surface topography can lead to a reduced process window (PW) of critical immersion levels. For a metal routing level near the top of the die stack, up to ~240 nm of topography can be present at immersion photolithography levels. In tight pitch regions of the metal routing layout, topography variations can cause poor printing, particularly near locations where the metal routing bends due to various layout constraints. Edge progression and corner jog layout optimization provide a solution to this less-discussed challenge in the 3D NAND fabrication process. Simulation results show a 70% increase of the PW in the areas where edge progression was applied. In bending regions of the metal routing, jog optimization improves the PW by 40%. These two layout optimization techniques increased the overall metal routing PW by ~40%, and this increase was validated by wafer FEM data. Additionally, the same jog optimization and edge progression techniques can be used to fix hot spot areas due to process variations. This paper presents a solution to compensate for the decreased PW of the metal routing level near the top of a 64-tier 3D NAND die due to fab topography issues through corner jog and edge progression layout optimization.
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Jennefir L. Digaum, Hung-Eil Kim, Eric Christensen, Hamilton Sanchez, and Moydul Islam "Full-chip layout optimization for photo process window improvement of 3D NAND metal routing level", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620K (20 March 2019); https://doi.org/10.1117/12.2512567
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