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5 April 2019 EUV mask synthesis with rigorous ILT for process window improvement
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The difficulties involved in ramping EUV lithography to volume manufacturing have highlighted the critical task of understanding process, layout design and device interactions, and also of optimizing the overall product integration to reduce undesirable interactions. In this paper, we demonstrate mask synthesis methods that using rigorous EUV lithography models together with inverse lithography technology (ILT) for EUV process window and CD control improvement. To enable this new capability, we have linked the broad EUV physical effect modeling capability of our rigorous lithography simulator, Sentaurus Lithography (S-Litho), with our highly flexible production proven ILT mask synthesis solution (Proteus ILT). This new combined capability can take advantage of the wide range of EUV modeling capabilities including rigorous electromagnetic mask/substrate modeling. The advantages of using S-Litho rigorous simulation for ILT optimization is further benefited from significant speed enhancements using new high performance EUV mask 3D capabilities. ILT has been extensively used in a range of lithographic areas for DUV and EUV including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies therefore will have a wide range of useful EUV applications. We will highlight the specific benefits of the rigorous DUV and EUV ILT functionality for several advanced applications including resist profile optimization for resist top- oss and resist descumming and process window improvement.
Conference Presentation
© (2019) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Kyle Braam, Kosta Selinidis, Wolfgang Hoppe, Hongyuan Cai, and Guangming Xiao "EUV mask synthesis with rigorous ILT for process window improvement", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 109620P (5 April 2019);


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