This PDF file contains the front matter associated with SPIE Proceedings Volume 10963 including the Title Page, Copyright information, Table of Contents, Introduction, and Conference Committee listing.

Etch processes have always involved inherent process trade-offs related to fundamental plasma parameters to achieve planar patterning metrics related to damage, aspect ratio dependences and profile. Today, we are in a new era of “area selective etch.” Advanced patterning (SAXP, (LELE)n), logic, memory and interconnect applications beyond 3 nm involve, in one way or another, topographies that require etch “control” at every surface. Achieving profile specifications will require the ability to conjure isotropy control at will. Vehicles to achieving this include novel precursors and hybrid processes involving combinations of deposition and plasma etch as we know it. Ultimately, to differentiate surfaces comprising silicon, silicon oxides and nitrides, and organics require active modification at the first surface reactive monolayer to be able to differentiate them in each process step with respect to any surface normal on the wafer plane. This presentation will start with a review of today’s state-of-the-art means for atomic precision processing of surfaces. A simulation science perspective to process integration modeling introduces methods for surface chemistry control that lend themselves to achieving area selective etch. In the end, surface chemistry control is not a cure-all. Finally, a combination of plasma diagnostics and simulation will be needed to assist plasma process controls for scaling at 3 nm and beyond.

With increasing challenges in reducing power density while keeping and even increasing the device performance at every new technology node, innovations in both the device architecture and materials will be needed to ensure continuous improvements in power, performance, area and cost. For the last decade, replacing the Si channel by higher mobility materials like III-V and (Si)Ge has been considered as one of the most challenging innovations needed to further scale down the supply voltage and improve the overall energy efficiency of CMOS circuits. While these materials will not only contribute to enhancing the standard CMOS performance, the possibility of integrating these materials on a Si platform opens exciting new opportunities to build unique circuits, systems and applications. Especially in RF applications, co-integration of III-V/GaN and Si CMOS might be the key enabling technology to provide the speed and power efficiency required for next generation mobile communications. While the device architectures under consideration differ from nowadays ultra-scaled FinFET and nanowire/nanosheet technologies, and their scaling in general is more relaxed, there are significant challenges related to integrating these components on Si substrates. It will need innovations in patterning, deposition and cleaning, next to addressing the challenges of handling these novel materials in a standard CMOS environment. In this work, we will review the status and integration challenges of these materials for both advanced CMOS technologies and RF applications. Focus will be put on the required advancements in etch and deposition needed to enable the integration of these novel materials and devices on a Si platform.

Extreme ultraviolet (EUV) lithography, using 13.5 nm radiation, is a prominent candidate for next generation manufacturing. Our main effort has recently focused on metal organic cluster photoresists, including both Zr and Hf metal oxides, both relatively low EUV absorbing metals. However, integration of high EUV absorption elements is now considered to be a more promising route to further improve lithographic performance under EUV radiation. Here, we report lithography of zinc oxide-based metal organic cluster photoresists, and EUV patterning below 15 nm. The lithographic performance of this and other metal oxides is described and etch characteristics discussed.

Due to the difficulty in scaling overlay commensurate with the required CD reduction, self-alignment schemes are becoming more and more pervasive. To enable such schemes, there is a need to have materials that have different etch selectivity (“colors”) compared to the standard Si, SiO2, SiN and C commonly available today. Development of novel materials with excellent conformality is needed to enable such “multi-color” material schemes. Plasma enhanced chemical vapor deposition (PECVD) has been used to deposit a wide range of dielectric films whose composition can be modified for etch selectivity. But these films are limited to planar applications. With topography, conformality becomes a critical requirement, along with the ability to tune material properties. Atomic layer deposition (ALD) is the method of choice for depositing conformal silicon oxides and nitrides thin films but has difficulty in tuning film composition or depositing films containing Si-C bonds. Lam Research has pioneered a new deposition technique, called SPARC, that fills this void between what PECVD and ALD techniques can deposit. This approach enables deposition of highly conformal, dense silicon oxy-carbide (SiCO) thin films, which are used as low-k spacers in both Logic and DRAM devices. The technology enables films with uniform infeature composition, and unlike ALD, lends itself to easy tuning of film composition to optimize etch selectivity for a desired application. In addition to SiCO, the same approach was then used to develop highly dense and conformal silicon carbon nitride (SiCN) films, again with the ability to tune composition. It is demonstrated that Si-C content is the primary driver for selectivity in both these film types. The unique capabilities of the SPARC deposition to access high quality silicon-based films has resulted in its implementation in both logic and memory device manufacturing. This deposition method can also extend to depositing novel materials. For instance, high-quality conformal boron-based films, such as boron carbide (BC) and boron carbon nitride (BCN), have been deposited and show different sputtering and etch behavior than the Si-based counterparts. For this reason, BC or BCN based films could add a distinct etch solution for advanced patterning. More broadly, the wide range of conformal films and compositions possible with this technology makes SPARC a unique asset to address etch selectivity requirements of advanced integration schemes.

With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter, driving requirements for on-product overlay performance below 2.5nm and CD uniformity requirements below 0.8nm. Achieving such performance levels will not only need performance optimization of individual tools but a holistic optimization of all process steps. This paper reports on the first step towards holistic optimization – co-optimized performance control of scanner and etch tools. In this paper we evaluate the use of scanner and etcher control parameters for improvement of after final etch overlay and CD performance. The co-optimization of lithography and etch identifies origins of the variabilities and assigns corrections to corresponding tools, handles litho-etch interactions and maximizes the correction capability by utilizing control interfaces of both scanner and etch tools in a single control loop. The product aims to improve total variability measured after etch as well as fingerprint matching between tools. For CD control we co-optimize the dose corrections on the lithography tool with the temperature corrections on the etcher. This control solution aims to correct CD variabilities originating at deposition, lithography and etcher. For overlay we co-optimize the overlay inter and intra-field grid interfaces on the scanner with the wafer edge ring height compensation on the etcher. The evaluation of both CD and overlay control solutions is performed for the 2xnm DRAM node of SK hynix DRAM group. YieldStar in-device metrology after core etch was used for CD control. On wafer verification showed an improvement of 23% of the total CD variation. In-device metrology after final etch was user for overlay control. Evaluation showed 35% improvement in total overlay variability due to scanner-etch co-optimization.

Uniformity of critical dimensions (CDs) across a wafer is an increasing challenge as both CDs and tolerances shrink. Plasma etch uniformity is achieved in part through reactor design and in part through the operating conditions or process recipe of the reactor. The identification of a recipe for a specific etch process is time consuming and expensive, requiring extensive experiments and metrology. Here we present two modules in SandBox StudioTM, SB-Bayesian and SBNeuralNet, to accelerate the prediction and optimization of etch recipes for across the wafer uniformity. A model of etch rates across the wafer is created that accounts for injector locations, gas flow rates and distribution and plasma powers. Synthetic experiments on etching line-space patterns on 300 mm wafers are performed and the CDs and their variations are computed at several hundred site locations. SB-Bayesian requires many fewer experiments to be calibrated and achieve an excellent qualitative match with the experimental data. SB-NeuralNet achieves comparable levels of accuracy to SBBayesian at predicting average CDs and uniformity, but it does not perform as well at predicting trends across the wafer. It is shown that neural nets require a prohibitive amount of experimental data to successfully predict wafer patterns. SBBayesian and SB-NeuralNet were used to create detailed process maps across the parameters space of interest to identify optimal recipes to achieve required CDs and tolerances. Both modules can predict optimal recipe conditions for achieving identified target CD and uniformity metrics. Using these tools, etch recipes for across the wafer uniformity are rapidly optimized at lower cost.

Plasma etching requires the nanometer scale precision control of the etched structures without particle generation which is a key factor of the defect and the yield ratio. Nevertheless, process drifts [1] and particles flaking off from the chamber wall are frequently observed in case of non-volatile metal accumulation on a chamber wall, because cleaning of metal by-product is more difficult than other by-products such as silicon and carbon. R Ramos et al [2] have reported the effective cleaning to reduce AlFx residue. However, sometimes, an etching of non-volatile chamber wall materials such as Al2O3 and Y2O3 at the same time by metal cleaning chemistries becomes the root cause of the particle and decreasing MTBC(mean time between clean). Therefore, it is important not to generate particles flaking off in mass production. In this study, effective AlFx cleaning was evaluated without chamber wall damage by microwave ECR plasma etching system. At first, effective AlFx cleaning was quantified by using in-situ FTIR equipment attached to the chamber side wall. The FTIR data showed that BCl3/Cl2 chemistry was higher cleaning efficiency than other chemistries such as Cl2, SiCl4/Cl2 and SF6/O2 for removing AlFx residue as mentioned previous study [2]. Second, Al2O3 etch rate distribution were measured using Al2O3 coupon sample simulating AlFx deposition. In this experiment, Al2O3 coupons were set in different locations such as top plate, sleeve and susceptor near the wafer stage. One of the unique characteristics of ECR plasma is that plasma generation position (ECR height) is movable by changing solenoid coil setting. After exposing BCl3/Cl2 plasma with two kinds of ECR heights at 146.8 and 197.2 mm from ESC (Electrostatic chuck) position, Al2O3 etch rates were measured. High ECR plasma (197.2 mm) showed higher Al2O3 etch rate at high chamber location such as top plate, while low ECR plasma (146.8 mm) showed higher Al2O3 etch rate at lower chamber location such as sleeve and susceptor. The scanning ECR height improves clean uniformity in the chamber. Also, ECR plasma has an advantage in reducing chamber wall damage by spattering non-volatile chamber wall materials with plasma to be able to control ECR height away from chamber walls. To evaluate long-term process stability of BCl3/Cl2 cleaning, marathon tests of 500 alumina wafers were executed. The Al2O3 wafers were etched by fluorine-based gas chemistry to generate AlFx residue. The two kinds of plasma cleaning every three Al2O3 wafers were evaluated. One was BCl3/Cl2 cleaning and the following SF6/O2 cleaning. The other was only SF6/O2 cleaning. As a result, particle count was stable during 500 wafers with BCl3/Cl2 cleaning while particle increased after 200 wafers without BCl3/Cl2 cleaning. The increased particle component was mainly Al. Therefore, the ECR plasma with scanning BCl3/Cl2 metal cleaning which could remove Al2O3 at the every corner, enables us to increase MTBC in etching mass productions including metal residues. References. [1] Kosa Hirota, et al, J. Vac. Sci. Technol. A 32(6)，61304 (2015). [2] R Ramos, et al, Plasma Sources Sci. Technol. 16, 711-715 (2007).

In patterning etch processes, the fabrication of multilayer films requires the precision of atomic scale X-Y CD controllability in complex hole patterns, and reduction of local variability such as Line Edge Roughness (LER), Line Width Roughness (LWR) and Local CDU (LCDU). In order to solve these requirements, we have developed Advanced Quasi-ALE technology which achieved reduction of LCDU, along with a wider X-Y CD control margin. In this paper, we introduce the three benefits of our atomic scale CD and variability control process technology; (1) XY CD control in oval patterns, (2) LCDU reduction and (3) wider etching window using Advanced Quasi-ALE technique. Hence, we will show that it has a significant potential to solve critical challenges in the patterning processes of N5 and beyond.

The latest advances in Machine Learning (ML) produce results with unprecedented accuracy, and could signal a new era in the smart manufacturing field. We propose a framework designed to work alongside experts: learning from them and optimizing their knowledge. This framework must be considered as a tool to assist the experts in their daily work. The user creates a measurement recipe which includes an example of the feature as well as the measurements placed by the process engineer. Grouping the measurement recipes of the same object in an entity collection allows the user to train a machine learning recipe which includes a deformation model to handle variations in structure and contrast. The new images are analyzed following the machine learning pipeline which includes the detection of features, repositioning, measurement, quality evaluation and finally the results of measurement are given to the user. We discuss the pipeline and we focus on the metrics to validate the machine learning recipe, providing quantitative results for stability and robustness to variations.

Within the world of integrated circuit manufacturing there is a continuous effort to increase device density in order to improve speed, performance and costs. Current technology is driving a transition from devices that use a planar transistor to a more “3D” design, such as with nanowires or even vertically oriented transistors. The fabrication of nanowire devices demonstrates a good example of 3D etch challenges where both anisotropic and highly selective isotropic etch processes are needed. Alternating Si and SiGe layers are first etched vertically, then are later recessed selective to one another. There are a number of literature reports which have demonstrated the capability of recessing SiGe selective to Si, however the opposite is not as well established. The key challenges of this task are maximizing the selectivity to the SiGe layers as well as any other spacer and mask materials exposed on the wafer including SiO₂, Si₃N₄, SiOCN and SiBCN. In this work, we present a study of isotropic etching for Si selective to SiGe in CF₄/O₂/N₂ and NF₃/O₂/N₂ based plasmas with selectivities higher than 50:1 achieved. Potential selectivity mechanisms are based on preferential oxidation of mixed SiGe layers opposed to Si, while formation of the NO molecule can result in excessive oxide layer removal from the Si surface.^1,2 A qualitative model is put forth to describe the resulting etch profiles using this chemistry. Supporting data regarding F:O ratio, temperature, and Si layer thickness dependency are shown in efforts to support the model. These results will provide essential insight as the industry decides which process solution is optimal for GAA devices.

The continuous driving force from the semiconductor industry for realizing smaller features and device structures with higher density and higher-aspect ratio poses increasing challenges in traditional etching techniques. Atomic layer etching (ALE) provides the opportunity to overcome the shortcomings of more conventional etching processes. Extensive research in this field has led to the development of two main classes: plasma ALE to achieve anisotropic etching and thermal ALE for the isotropic counterpart. Besides anisotropic etching, plasma can also be applied for achieving isotropic etch profiles. Yet, this process option has not been explored extensively. In this work, we demonstrate isotropic ALE of ZnO on a regular array of vertical nanowires, using the alternated doses of O2 plasma and acetylacetone (Hacac). A linear ZnO thickness decrease with increasing number of cycles was measured by in-situ spectroscopic ellipsometry, and saturation behavior was demonstrated for both Hacac and O2 plasma, at 250 oC. The etch rates per cycle were found to increase from 0.5 to 1.3 Å/cycle with process temperature increasing from 100 to 250 oC. Transmission electron microscopy (TEM) studies conducted on ZnO-coated nanowires before and after ALE proved the isotropic character of the process. Moreover, the ALE process produced no surface damage as concluded from high resolution TEM inspection. In-situ infrared spectroscopy measurements were conducted to elucidate the mechanism underlying self-limited etching. Based on these measurements, a preliminary reaction mechanism is proposed, in which Zn(acac)2 is assumed to be the etching product and persisting acac-species on the ZnO surface provide the self-limiting character. Finally, a high etch selectivity over SiO2 and HfO2, and the possibility to extend the process to other oxides such as Al2O3 are also demonstrated. We believe that this plasma-based ALE process represents a valuable addition to the ALE toolbox and opens-up new possibilities for using plasma-processing to achieve isotropic etch profiles. Furthermore, similar approaches can be used to extend the process to other materials by tuning the plasma chemistry accordingly.

As process technology progresses beyond the 7 nm node, the critical dimension uniformity (CDU) requirement is now in the sub-1 nm regime due to patterning complexity or smaller patterning size. In this report, across-wafer CDU improvement by etch tool correction using the Hydra uniformity system in an advance Lam Research etch tool for a 7 nm FEOL logic application is discussed. The results show that CDU is improved by 60% compared to baseline performance of 3σ < 1 nm, and the post etch CDU is comparable to the ultimate target CDU of post EUV litho development. In conclusion, superior post-etch across-wafer CDU is achieved using the Hydra uniformity system by correcting local non-uniformity after the radial contribution is reduced by traditional multizone ESC tuning.

Despite the innumerable advances in EUV lithography for materials, optics, and process in recent years, the N7 and N5 targets for resolution, line roughness, and sensitivity (RLS, collectively) have not simultaneously been achieved from both a yield and cost perspective due to their interdependent nature. For example, reducing dose to an economically practical level results in resolution and roughness levels that generate unacceptable yield and performance. These limitations have traditionally been viewed in a light where only conventional post-lithographic processing by etch is used for the subsequent pattern transfer. Recent post-lithography defect mitigation techniques, however, combine the use of high etch selectivity underlayers, atomic layer etch (ALE) descum, and fast-switching deposition and etch resist linespace pattern repair have overcome the limitations of the RLS interdependency by correcting for resolution and stochastics related defects and improving LER associated with lower exposure dose [1]. Here, an aspect ratio dependent deposition can be used to protect the resist lines from further notching and damage while allowing for residual scum between the lines to be etched [2]. A lithography, etch, and metrology feedback loop can be envisioned in which a minimum dose requirement is found where both the LER and lithography related defects are still correctable using post-exposure processing; however, due to the extremely long metrology times for e-beam inspection combined with the large quantity of adjustable parameters, traditional experimental DOEs quickly become unmanageable. The intractability of this situation necessitates a simulation-based parameter space optimization to reduce the required number of feedback cycles. In this study, Coventor SEMulator3D® is used to find optimized solutions for minimizing resist line bridges and breaks as well as line smoothing. Here, distributions of line roughness and resist divot and scum dimensions can be subjected to simulated process recipes with tunable parameters like etch selectivities, aspect ratio dependence of deposition and etch, deposition and etch rates, number of ALE cycles, etc. that one would typically explore in this defect mitigation strategy. The resulting defects can then be analyzed to determine how each defect in the distribution reacts to a given treatment. Additionally, further insight can be gleaned regarding the types and dimensions of defects that can be corrected and that would otherwise not be measurable using any physical metrology. For example, at low dose, a portion of the defect size distribution is comparable to the drawn features and can no longer be corrected by the post-exposure treatment. Due to the randomness of the defects and small size, three-dimensional characterization is difficult, but using simulation, it is possible to show at what dimension the defect mitigation strategy begins to fail.

TEL’s patented DCS function and conventional plasma treatment were applied on EUV PR to examine the effect of ion/radical loading and surface modification. The DCS function accelerates plasma selective deposition particularly on the top of EUV PR at 36nm pitch. The increment of EUV PR height secures etching budget and provides longer plasmas smoothing period. In addition, line roughness was also smoothed during area plasma selective deposition due to loading effect. In this study, our plasma treatment was able to improve PR roughness by 30% comparing to as-exposed litho and the performance was kept to the next oxide layer. Furthermore, an extra 13.7nm of PR was gained which enlarged the process windows of etching selectivity and plasma smoothing effect.

Area scaling without compromising on performance has become a challenge for technology nodes beyond N7. Gate all-around (GAA) device architecture for N5 and beyond technology nodes is emerging as a promising solution and is being heavily investigated by the semiconductor industry. Imec has recently demonstrated that GAA transistor design offers 50% area scaling for both standard cells and SRAM memory cells, by stacking NMOS and PMOS wires on top of each other (also called complimentary FET (CFET)). In addition, design technology co-optimization analysis indicates that CFET architectures meet the N3 power and performance requirements (Ryckaert et.al.; SPIE 2018, VLSI technology symposium 2018). However, integration and fabrication of such CFET architectures become significantly challenging. A primary requirement for GAA (CFET or separate NMOS/PMOS) devices is the formation of silicon channels / nanowires (NW)/nanosheets (NS). For CFET fabrication, a quintessential challenge is an etching method which can provide required selectivity to recess an epitaxially grown material selective to either NMOS or PMOS channel materials into a low-k gate spacer with adequate etch selectivity in an isotropic manner such that stacked wires or sheets can be formed either sequentially or simultaneously. In the article, we will focus mainly on the Si NW/NS formation (or SiGe etch). Fabricating such NW/NS architecture requires two extremely selective, isotropic, and precise SiGe etches. As shown in Fig.1, step 2 (“SiGe cavity etch”) & step 8 (“channel release”). After the “SiGe cavity etch”, an ALD film of low-k spacer is deposited as the inner spacer (Fig.1, step 3). The SiGe cavity etch (Fig.1, step2) must be controlled with an extreme accuracy and have a straight etch front. The cavity etch will effectively define the inner spacer thickness in the area above and below the Si NW, after the inner spacer etch (step 4, Fig.1). A precise SiGe etch control is essential for the cavity formation, because: (1) if the SiGe recess is below target, the reformed inner spacer thickness will be under specification and may result in high parasitic capacitance between gate and source/drain expected. (2) If the SiGe recess is above target, the reformed inner spacer will penetrate into the replacement gate and will decrease the amount of gate metal wrapping around the nanowire and may impact channel length (Lg). Furthermore, in addition to the above requirements, etch selectivity towards the dummy gate, hard mask, oxide (STI, ILD0), and low K material around the gate (as shown in Fig 1) is essential. We will also demonstrate the process performance for “channel release” as mentioned earlier (Fig 1, step 8) and inner spacer etch (Fig 1, step 4) .To address the requirements described above, a process flow enabled with extremely high selective etches, where the selectivity is a function of film properties and/or etch chemistry is a quintessential advantage. In this article, we will demonstrate the significance of such selective etches for Si NW/NS fabrication.

This study provides a new chemistry composition as an effective etchant with a plasma-less dry process for selectively etching Si₃N₄ to SiO₂ with selectivity over 200. Both blanket and patterned wafers were examined. To investigate the parameters affecting selectivity, blanket wafers were tested. Etch rate and selectivity can be optimized by tuning the etchant concentration, chamber temperature and chamber pressure. The selectivity can be tuned from 10 to over 200 depending on the testing condition. It was found nearly etch stop of SiO₂ with increasing the etching time, leading to higher selectivity with increasing the processing time. Under the optimized condition, etching rates of Si₃N₄ > 30 nm/min and SiO₂ < 0.2 nm/min were obtained. It was also demonstrated on 3D-NAND patterned wafers of ONON stacked layer with pre-etched holes. The Si₃N₄ layers can be removed with lateral etching rate >20 nm/min, while maintaining the SiO₂ layer.

Metasurfaces are optical elements with nanoscale dimensions and planar profiles that expand the functionality and usefulness of traditional refractive optics. This has lead to considerable interest in metasurfaces for a variety of applications, including consumer electronics, automotive, and medical devices. Metasurface elements can be manufactured using standard microelectronics process techniques enabling mass production of optical elements in semiconductor foundries. Additionally, being produced at the wafer-scale, metasurfaces enable wafer-scale integration of optical systems. However, most metasurfaces to date have been produced in small-scale research settings using serial patterning techniques such as electron beam lithography. In order for metasurfaces to penetrate high volume applications, scalable production processes must be developed, including lithographic reproduction of metasurface design geometries. In particular, the constituent elements of metasurfaces, nanopillars, have shapes, aspect ratios, and local density variations which diverge from typical microelectronics design rules. After a brief overview of metasurface fundamentals and their applications we will discuss traditional fabrication techniques, device requirements, and the challenges that arise when scaling to manufacturing. We will also discuss future generations of metasurfaces and further challenges in terms of geometry, critical dimensions, and materials compatibility.

With the diminishing PPAC returns from dimensional scaling of CMOS technologies, new avenues to maintain the scaling roadmap need to be explored. Design-Technology Co-Optimization has succeeded in leveraging specific integration techniques to alleviate scaling bottlenecks of some critical design rules both in SRAM as well as logic cells. Unfortunately, these building blocks are now reaching records in compactness reducing the amount of integration opportunities to enhance their further scaling. The 3rd dimension has been seen for a long time as a holy grail that could unlock many design constructs bottlenecks in advanced CMOS technology nodes. Many of these attempts have failed in providing a universal solution for CMOS platforms. However, an optimal usage of the 3rd dimension can be found in some specific cases by a careful understanding of the design context. We will review in this talk few 3D CMOS integration techniques that offer new scaling opportunities for future technology nodes. Among these approaches we will explore the usage of buried interconnects for power delivery, the use of vertically oriented FETs for on-chip memory as well as a disruptive device built out of the stack of a pFET and an nFET into a single structure called CFET. In the latter, we will explore its scaling potential as a means to position it as a future general purpose device solution for CMOS logic as well as SRAM.

Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary (‘standard’) integration scheme uses SiO₂ CP, Si₃N₄ GP and SiCO SWS. Furthermore, we investigate the “alternative’ integration scheme with SiCxNy films as replacement of the traditionally used SiO₂ CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO₂ or SiC_xN_y) towards Si₃N₄ and SiCO; as well as for GP (Si₃N₄) plasma dry etch process towards SiO₂ or SiC_xN_y and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO₂ etch process is developed with a selectivity of 8 to 1 towards Si³N₄ and SiCO. For the selective Si₃N₄ etch continuous wave plasma CH₃F-based process is developed and selectivity of 9 to 1 towards SiO₂ and SiCO achieved. In the case of the integration scheme with SiC_xN_y CP, the selectivity for SiC_xN_y etch towards Si₃N₄ GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF₃/O₂- based process. As for the Si₃N₄ plasma etch in the ‘alternative’ scheme using CH₃F/O₂-based process, the selectivity towards SiC_xN_y of higher than 20 to 1 and selectivity to SiCO of around 10 to 1 is achieved.

This paper uses Virtual Fabrication to assess the imec 7 nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16 nm half-pitch Metal 2 line formation. We present first the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a <1% failure rate using a combination of Advanced Process Control and Virtual Fabrication.

Device size shrinkage has been one of the most effective methods in the semiconductor industry for the purpose of cost reduction and performance enhancement. In order to achieve the size requirement at the nanometer level, there are several patterning techniques, such as extreme ultra violet lithography and self-aligned multi-patterning, which have attracted intensive attention from the industry. One of the most popular patterning methods is self-aligned multiple patterning (SAMP). This method relies on self-alignment of a sidewall spacer to transfer into desirable patterns. After transferring, the resulting patterns will have half the pitch of the original structure. The process can be repeated for additional pitch halving in term of size shrinkage. This method has been adapted for high volume production in the advance semiconductor technology node for the past several years. It provided supreme performance in terms of physical performance such as line width roughness (LWR) and critical dimension uniformity (CDU). However, due to the process complexity, this technique usually suffers the pitch walking effect and relatively high cost and long turn-around time compared with the direct patterning method. In this paper, we studied several integration flows for sub-30nm pitch line and space including 193i SAQP and EUV SADP schemes. A general cost analysis is performed to compare the differences in cost and number of processing steps. Besides the manufacturability, we summarized a comprehensive line and space performance comparison between these flows in term of physical performance (CD, LWR, LER and SWR) and the potential impact factors for pattern process control such as sidewall angle and step height.

A methodology is presented to virtually predict etch profiles on flexible substrates across multi-dimensional process spaces using a minimal number of calibration experiments. Simulations and predictions of the physics and chemical kinetics of plasma etch on flexible substrates are performed using the commercial software SandBox StudioTM. The evolution of a trench profile is computed using surface kinetics models and the level set method. Local etch rates include visibility effects to account for partial shielding of the etch as the pattern is developed and the effects of redeposition. The results of the experiments are then used to update the calibrated model parameters. If the process objectives (e.g., sidewall angle, trench critical dimensions, and across the web uniformity) are not achieved, then a new set of experiments is suggested by the methodology. The process is repeated until the optimal process conditions are identified. The methodology is validated by experiments on etching line-space patterns of polysilicon films on polymer substrates. Results with reactive ion etching with either CF₄ and HBr are shown and the optimal etch recipes (power, etch time and gas flow rates) determined. It is found that this coupled simulation-experiment approach is much more efficient than full factorial experimental design at predicting process outcomes. The methodology presented requires 66% fewer experiments reducing the cost of development by a factor of three.

Astronomical X-ray diffraction gratings are a key technology under development for current and future NASA missions. X-ray reflection gratings, developed at Penn State University, have recently demonstrated both leading diffraction efficiency and high spectral resolving power. However, recent results are the result of different fabrication techniques and a single technique has not yet been developed to yield a grating that satisfies both the diffraction efficiency and resolving power required by future missions. Here we seek to leverage exiting electron-beam lithographic techniques to produce a grating with groove groove pattern capable of high resolving power. We then introduce new ion-milling techniques to create custom groove profiles capable of high diffraction efficiency. The goal is to produce a radial groove pattern with precisely blazed facets that are customizable based on ion mill input parameters. The process should be insensitive to groove density (ranging from ~150 nm to 400+ nm), facet size, and desired facet angle. Initial efforts in this study have concentrated on constraining various parameters in ion milling to fully characterize the effect of each parameter on the grating groove profile. We present here initial results and discuss experimental verification and future work.