Paper
7 May 2019 Fabrication of high aspect ratio bumps for focal plane arrays applications
Wei Zhang, Paul Bereznycky, Manuel Morales, Wei Huang, Doug Malchow, John Liobe, Scott Endicter, Michael Caro, Michael J. Evans, Sean Houlihan
Author Affiliations +
Abstract
For ultra-fine pixel pitch focal plane array (FPA) applications, flip-chip hybridization has advantages including high I/O density and short distance between the photodiode array (PDA) and the readout integrated circuit (ROIC). Indium has become the primary interconnect material because of its high ductility at low temperature. Successful mating of large format die becomes increasingly difficult, however, for finer pitch applications where bumps are shorter, as tolerance for bowing is low. Simultaneously, the epoxy filling process for large image format, hybridized focal planes becomes more challenging. These constraints call for tall indium bumps with high aspect ratio to accommodate die bowing and provide larger openings for the flow of fill epoxy. A process for the fabrication of highly uniform, high aspect ratio (height:diameter) indium bumps has been developed by Sensors Unlimited Inc. (SUI), a Collins Aerospace Company. The grain size of the deposited indium metal is minimized by optimizing process parameters as well as introducing intermediate metal layers underneath the indium bumps. Anisotropic deposition has been achieved by optimizing deposition rate and controlling substrate parameters. Indium bumps with aspect ratios over 2:1 and flat bump heads have been achieved. The developed bump process has been successfully applied to the fabrication of high resolution indium gallium arsenide (InGaAs) FPAs. Key control parameters for bump formation will be discussed in this paper.
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Wei Zhang, Paul Bereznycky, Manuel Morales, Wei Huang, Doug Malchow, John Liobe, Scott Endicter, Michael Caro, Michael J. Evans, and Sean Houlihan "Fabrication of high aspect ratio bumps for focal plane arrays applications", Proc. SPIE 11002, Infrared Technology and Applications XLV, 110022F (7 May 2019); https://doi.org/10.1117/12.2519202
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KEYWORDS
Metals

Indium

Readout integrated circuits

Deposition processes

Coating

Semiconducting wafers

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