High-speed photonic CMOS technology for logic and memory applications

James N. Pan

doi:10.1117/12.2524557

3 September 2019 High-speed photonic CMOS technology for logic and memory applications

James N. Pan

Proceedings Volume 11089, Nanoengineering: Fabrication, Properties, Optics, Thin Films, and Devices XVI; 110891I (2019) https://doi.org/10.1117/12.2524557
Event: SPIE Nanoscience + Engineering, 2019, San Diego, California, United States

Abstract

This paper reports a novel optoelectronic sub-7nm CMOS transistor, which can be fabricated with a multiple quantum well (MQW) laser or tunnel light emitting diode (TLED) in the drain region, and an underlying avalanche breakdown photo diode (APD). The CMOS, photonic device, and APD are integrated as one transistor. The methods described in this report are fully compatible with a conventional CMOS process flow, including the FINFET technology, and scalable for future sub-10nm technology nodes. The Ion/Ioff ratio may surpass 10nm CMOS with these additional optoelectronic components.

Citation Download Citation

James N. Pan "High-speed photonic CMOS technology for logic and memory applications", Proc. SPIE 11089, Nanoengineering: Fabrication, Properties, Optics, Thin Films, and Devices XVI, 110891I (3 September 2019); https://doi.org/10.1117/12.2524557

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