The 3DCM734 (monochrome) and 3DCM739 (RGB) cameras have been designed based on the 3D PLUS technology and comprises 4 stacked levels in order to obtain a 3D cube with a reduced volume of 35x35x25 mm3 and a weight of 62g. The top level contains the CMOS image sensor (same as CIS1 defined in ) which is the key element of the camera. The CMOS sensor is constituted by 2048 x 2048, 5.5µm-pitch pixels. Each pixel is based on pinned photodiode  architecture with several transistors. The sensor is fully digital, it contains an on-chip microcontroller, registers, per column ADCs (2048) and can be read using 16 Low Voltage Differential Signaling (LVDS) outputs. The behavior of the digital part of the sensor against Single Event Effects (SEE) has been evaluated by CNES  and shows low upset events and the need for a protection against Single Event Latchup (SEL) . Red, green and blue color filters are introduced in the optical stack above each pixel using a Bayer array distribution. Microlenses are deposited on the top of each pixel at the end of the image sensor process. This optical element focuses the incident light in the pixel to improve the pixel quantum efficiency.
The Field Programmable Gate Array (FPGA) has a 3.000.000 system gates capacity and uses a low power technology, latchup free and radiation tolerant up to 50krad(Si). It is located on the second level aiming to interface the sensor with the instrument system. The FPGA can store images in the volatile memory placed on the same level and perform preliminary image processing as averaging, adding, windowing etc… Non-volatile memories are also included to load the register state of the sensor and the star catalogue in case of star tracking requested.
A serial interface is used to sending commands to the camera, LVDS interface is used for camera output. FPGA can be suited by the user to the system needs by modifying its programmation code. An oscillator provides the clock signal to the FPGA.
A 1G x 8bits non-volatile flash NAND memory is used to store reference pictures or cartography.
A 128M x 8bits volatile SDRAM memory is used for image storing or processing.
The bottom of the camera contains a PGA array which is able to cover a wide range of connections, from LVDS to Space-Wire depending on the FPGA code.
The input voltage supply of the camera module is between 4.5V to 9V. Four different voltages (3.3V, 2.5V, 2.1V and 1.5V) are generated internally by four voltage regulators in order to feed the sensor, the oscillator, the FPGA and the memories (volatile and non-volatile).
Images are provided by the CMOS sensor through LVDS multiplexable outputs. The frame rate is dependent on the pixel mode :
The camera module has been fully characterized. Key electrical parameters are shown in Table 1.
|Operating Current @ 5V||Idd||0.4||A|
The CMOS sensor is sensitive to Single Event Effects as previously mentioned. The current limitation capability integrated in the module, is able to switch-off the power supply to the sensor in case of SEL or SET. Both « P3V3 SENSOR » voltage and « P2V1 SENSOR » voltage are monitored in order to protect the CMOS sensor as it can be depicted from Figure 4.
The principle of over-current detection is based on one comparator and a switch. In case of over-current, a signal (OCD3V3 or OCD2V1) is sent to the FPGA. Since the FPGA receives the command, acknowledges receipt, sending back the « PWR_SENS » signal and switches-off the lines. The FPGA sets to high impedance state all the signals connected to the CMOS sensor.
The second main function included is the Reset circuit which controls the 3.3V power supply. This circuits sends a “MRESET” command to the FPGA when the power supply is either over 3.2V or under 3.1V. The circuit is based on a voltage comparator and manages the delay before the activation of the “MRESET” command as it is shown in Figure 5.
3D PLUS STACKING TECHNOLOGY
The camera module has been designed and manufactured with 3D PLUS stacking technology. This 3D technology is based on the stacking of electronic components (chips, plastic packages, sensors) reported on a thin pcbs, and so called flex. This solutions allows testing and screening the components of each layer before stacking. This is the key feature for building ‘n’-High stacks with a very good yield. The flex are then stacked vertically and connected together thanks to a vertical interconnection technique.
This System-In-Packages (SiPs) technology allows gaining a factor of at least 10 on weight and volume of the components. It enables achieving a combination that cannot be realized with monolithic System-on-Chip (SoC) approaches. This capability domain is referenced as FLOW 2 and is qualified by European Space Agency (ESA) for Space applications.
The manufacturing process is shown in Figure 6.
QUALIFICATION AND RADIATION PERFORMANCES
The camera module (without the optics) and each basic component integrated in the camera have been qualified. Eleven cameras were selected to go through different test files. Thermal Cycles, Life Test and Temperature Humidity Test have been performed along with a DPA after each test. All tests passed successfully.
The camera module has been irradiated with a gamma beam produced by a Co-60 source. The dose rate emitted from the source was 210rad/h. Electro-optical measurements were performed after each irradiation step (1krad, 5 krad, 10 krad and 50 krad) and also after 24h (at 25°C) and 168h (at 100°C) annealing. The results showed that no significant impact on dark current and noise was observed. Two camera modules have been irradiated with protons in order to measure the degradation of the dark current due to the Displacement Damage Dose (DDD) and compare it to the one caused by the Total ionizing Dose (TID) . The efficiency of the SEL protections integrated in the camera have also been tested and the anti-latch-up systems works properly up to 62 MeV.
Three IP controllers specifically designed for the 3D PLUS CMOS Space Camera have been developed. These IP’s can be used as building blocks to develop a tailored code for any type of application.
3DIPCC0735-1 is an IP memory controller intended to be used with the SDRAM memory. It provides all functions of a standard SDRAM controller and data error management including an ECC and scrubbing mechanism. 3DIPCC0736-1 is the NAND Flash memory controller. It brings the capability to store all data provided by the sensor. 3DIPCC0737-1 is a unique IP controller conceived to manage the CMOS sensor. This code makes possible to get access to all sensor registers.
Also, a complete flight code (3DIPCC0746-1) has been conceived to be integrated into the 3D PLUS CMOS Space Camera modules. It provides an efficient interface to support camera applications and processing video data in a user-friendly manner. All internal memories are managed automatically as FIFOs and no addresses have to be managed by the user. This IP Core also brings the capability to operate the memories without having to focus on interfaces and especially on radiation mitigation mechanism. All codes have been developed in concordance with ECSS-Q-ST-60-02C ESA standard.
The camera module has been selected for the Mars2020 mission (NASA JPL) and a RGB version will be placed in the SuperCam scientific instrument (Mast Unit) developed by the IRAP (Institut de Recherche en Astrophysique et Planétologie) in collaboration with Los Alamos National Laboratory. The images of the martian surface that will be taken, will be used to analyze the chemical composition and mineralogy of the rocks. Another mission lead by the CNES, which is the EYE-SAT (JANUS program) nanosatellite will use the camera module for Earth and zodiacal light observation.
In addition to these two missions, the camera will make part of the PROSPECT’s drill (ProSEED) instrument that will operate at the surface of the Moon as part of the Russian-led Luna-27 mission in 2022. Other applications where the camera will be employed are star-tracking, spectropolarimetry and docking monitoring.
The authors wish to thank the detection chain team at the CNES for their support in the space camera development.
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