Scalability of silicon photonics packaging is required to support the growing demand for bandwidth in data centers and other emerging datacom and telecom applications. Connecting fiber to chip is still considered one of the main challenges of silicon photonics today due to the need for high alignment accuracy, which in turn requires expensive assembly machines and in most cases active alignment protocols. Furthermore, current fiber assembly technologies are not suitable for multiple emerging applications with large port count such as co-packaged optics. We present here the Photonic-plug technology, a unique self-aligning optical arrangement, which enables large assembly tolerance suitable for passive alignment protocols and for scalable silicon photonics port count packaging. The Photonic-plug technology accomplishes die stacking geometry with efficient wideband surface coupling as well as with grating coupler based silicon photonic chips. The combination of the Photonic-plug's large assembly tolerances and surface coupling geometry enables efficient silicon photonics wafer level testing capabilities prior to dicing. The Photonic-plug technology takes advantage from wafer level fabrication processes for planar and accurate implementing of optical elements. A library service model, called Photonic-bump, is incorporated as part of the Photonic-plug technology through silicon photonic wafer manufacturing process for complete removal of the fibers' mechanical constraints from wafer manufacturing process. The Photonic-plug takes fiber-to-chip packaging away from specialized, low throughput and expensive tools to standard, automated and high volume flip-chip packaging machines. Standardizing optical packaging through Photonic-plug methodology will affect further silicon photonics application to thrive such as photonic FPGA, optical interposers and chip-to-chip optical connectivity.