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31 January 2020 Design considerations for multi-chip module silicon-photonic transceivers
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Abstract
High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.
Conference Presentation
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nathan C. Abrams, Qixiang Cheng, Madeleine Glick, Evgeny Manzhosov, Moises Jezzini, Padraic Morrissey, Peter O'Brien, and Keren Bergman "Design considerations for multi-chip module silicon-photonic transceivers", Proc. SPIE 11308, Metro and Data Center Optical Networks and Short-Reach Links III, 113080I (31 January 2020); https://doi.org/10.1117/12.2544008
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