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23 March 2020 EUV OPC methodology for beyond 20nm memory cell by simulation data
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Currently advanced DRAM design is beyond ArFi resolution limit, especially for the challenging processes in memory cell and core circuit pattern [1]. When devices keep shrinking, multi-patterning with ArFi becomes more and more difficult to reach the process requirements in terms of pattern decomposition, process window loss with complex process integration, defect, and immersion resolution limits. Besides multi-patterning also suffers design cost, mask learning cycle and layout restriction. Currently 0.33NA EUV can provide 16nm pattern single exposure and cover all design circuit requirement. High resolution enhances 2D pattern process window for friendly layout design and better OVL control so it is a good choice to introduce EUV process for DRAM manufacturing.

We evaluate to apply EUV in memory cell instead of the two possible solutions of SADP with cut layer and LELE trimming with multi-mask to simplify processes. Memory cell is periodic main feature for the most area on a mask and dominates the most EUV OPC run time in full shot correction. In this paper we try to find a best way to handle cell area OPC and evaluate single mask to accomplish memory cell patterning.
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Jiunhau Fu, Chiang Lin Shih, Chun Cheng Liao, Eric Huang, Elsley Tan, John Tsai, Ming Yun Chen, Yuan Pin Liao, and Seung Hee Baek "EUV OPC methodology for beyond 20nm memory cell by simulation data", Proc. SPIE 11323, Extreme Ultraviolet (EUV) Lithography XI, 113232H (23 March 2020);


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