Understanding advanced DRAM edge placement error budget and opportunities for control

Jaeseung Jeong; Jinho Lee; Jinsun Kim; Sunyoung Yea; Chan Hwang; Seung Yoon Lee; Jeongjin Lee; Joonsoo Park; Peter Nikolsky; Daniel Park; Antonio Corradi; Hyun-Woo Yu; Sun-Wook Jung; Denis Ovchinnikov; Vadim Timoshkov; Isabel de la Fuente Valentin; Yuxiang Yin; Kaustubh Padhye; Wim Tel; Harm Dillen; Koen Thuijs; Daan Slotboom; Miao Wang; Rhys Su; Marc Kea; Jin-Woo Lee; Yun-A Sung; Sang-Uk Kim; Young-Hoon Song; James Lee; Oh-Sung Kwon

doi:10.1117/12.2551997

20 March 2020 Understanding advanced DRAM edge placement error budget and opportunities for control

Jaeseung Jeong, Jinho Lee, Jinsun Kim, Sunyoung Yea, Chan Hwang, Seung Yoon Lee, Jeongjin Lee, Joonsoo Park, Peter Nikolsky, Daniel Park, Antonio Corradi, Hyun-Woo Yu, Sun-Wook Jung, Denis Ovchinnikov, Vadim Timoshkov, Isabel de la Fuente Valentin, Yuxiang Yin, Kaustubh Padhye, Wim Tel, Harm Dillen, Koen Thuijs, Daan Slotboom, Miao Wang, Rhys Su, Marc Kea, Jin-Woo Lee, Yun-A Sung, Sang-Uk Kim, Young-Hoon Song, James Lee, Oh-Sung Kwon

Author Affiliations +

Proceedings Volume 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV; 1132506 (2020) https://doi.org/10.1117/12.2551997
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

In leading edge patterning processes, overlay is now entangled with CD including OPC residuals and stochastics. This combined effect is a serious challenge for continued shrink and can be characterized with an Edge Placement Error (EPE) budget containing multi-domain components: global and local CD, local placement errors, overlay errors, etch biases and OPC. EPE defines process capability and ultimately relates to device yield. Understanding the EPE budget leads to efficient ways to monitor process capability and optimize it using EPE based process control applications. We examine a critical EPE use case on a leading edge DRAM node. We start by constructing and verifying the EPE Budget via densely sampled on-product in-device local, global CD and Overlay metrology after the etch process step. EPE budget contributors are ranked according to their impact to overall EPE performance and later with simulated EPE performance improvements per component. A cost/benefit analysis is shown to help choose the most HVM-friendly solutions.

Conference Presentation

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Jaeseung Jeong, Jinho Lee, Jinsun Kim, Sunyoung Yea, Chan Hwang, Seung Yoon Lee, Jeongjin Lee, Joonsoo Park, Peter Nikolsky, Daniel Park, Antonio Corradi, Hyun-Woo Yu, Sun-Wook Jung, Denis Ovchinnikov, Vadim Timoshkov, Isabel de la Fuente Valentin, Yuxiang Yin, Kaustubh Padhye, Wim Tel, Harm Dillen, Koen Thuijs, Daan Slotboom, Miao Wang, Rhys Su, Marc Kea, Jin-Woo Lee, Yun-A Sung, Sang-Uk Kim, Young-Hoon Song, James Lee, and Oh-Sung Kwon "Understanding advanced DRAM edge placement error budget and opportunities for control", Proc. SPIE 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV, 1132506 (20 March 2020); https://doi.org/10.1117/12.2551997

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